How can engineers debug next-generation chip connections running at 128 GT/s? A test platform aims to expose protocol issues before they delay AI infrastructure development.
Keysight Technologies has introduced a protocol test solution for PCI Express (PCIe) 7.0, a high-speed interface used to transfer data between processors, accelerators, memory and other system components. The platform is designed to help engineers test and debug connections for AI infrastructure and data centres.
The solution aims to shorten debugging time, identify communication errors early and reduce costly redesigns. This is increasingly important as faster interconnects must support reliable data transfer between increasingly complex computing components.
PCIe 7.0 doubles the raw data rate of PCIe 6.0 to 128 gigatransfers per second (GT/s). At these speeds, engineers must verify not only whether devices connect successfully but also whether they exchange data correctly and respond properly to errors.
The platform combines a protocol analyser, an exerciser, a test backplane and analysis software. The analyser captures and examines communication between connected devices, helping engineers identify errors and trace their causes. The exerciser acts like a simulated device, generating test traffic and responses to check how the chip or system behaves under different conditions. The backplane connects the equipment under test, while the software helps engineers interpret the results.
Together, these tools support testing from initial silicon bring-up, when engineers first check whether a newly developed chip works, through interoperability and compliance testing. They also provide visibility into link training, the process devices use to establish a connection, and errors in data transactions.
Keysight collaborated with Synopsys to validate the latter’s PCIe 7.0 intellectual property using the test solution. Establishing a reliable connection between production silicon and test equipment is an important step towards verifying compatibility.
“Establishing a reliable PCIe 7.0 link at 128 GT/s between production silicon and protocol test equipment is a key interoperability milestone,” says Neeraj Paliwal, Senior Vice President, Silicon IP Product Management, Synopsys.
Click here for the official announcement.
