A new material, a cooler process, and a stacked design: MIT’s prototype points to a future where chips move data millimeters less and save orders of magnitude more energy.
In a development that could reshape how future chips are built, MIT researchers have demonstrated a fabrication technique that stacks logic and memory directly on top of existing circuits potentially slashing the energy wasted shuttling data across a chip. The advance, presented this week at IEDM 2025, points to a path for more efficient computation as AI workloads strain global power grids.
Today’s chips still separate logic and memory, forcing data to travel through long interconnect networks. That movementsimple electrons trekking micronscosts huge amounts of energy at scale. MIT’s new platform collapses that distance by building transistors and memory cells in tight vertical layers on the back end of a finished CMOS chip.
The breakthrough hinges on amorphous indium oxide, a material that can be deposited at around 150°Cgentle enough to avoid damaging the underlying circuits. This enables active devices to be added after standard fabrication, bypassing the high-temperature barrier that usually blocks 3D stacking.
The team refined the material to near-atomic precision, engineering a ~2 nm transistor channel with tightly controlled oxygen vacancies. Too many defects and the transistor fails; too few and it won’t switch. The optimized structure produces tiny devices that toggle rapidly while drawing less power than comparable silicon transistors.
Using the same low-temperature approach, researchers also built 20 nm memory transistors by adding a layer of ferroelectric hafnium-zirconium-oxide. These cells switch in ~10 nanoseconds/the limit of the team’s instruments while operating at far lower voltages than typical embedded memory. Their scale also lets researchers probe the physics of ferroelectric behavior at near-single-unit dimensions.
The group collaborated with the University of Waterloo to model device performance, a necessary step toward circuit-level integration.
The researchers say the platform could help rein in the soaring energy appetite of AI, deep learning, and computer vision hardware by dramatically shrinking the logic-memory gap. Next, they aim to integrate full memory stacks and push the performance limits of ferroelectric materials.
If successful, this back-end-of-line electronics approach could give chipmakers a new toolkit for denser, faster, and more power-efficient systems without rewriting the entire CMOS playbook.
