Texas Instruments has an alternative technology, called PowerStack, for 3D packaging. It involves stacking TI’s NexFET power MOSFETs on a grounded lead frame and connecting them using copper clips. This combination of stacking and clip bonding results in a more integrated quad flat no-lead (QFN) solution that delivers a smaller size, better thermal performance, higher switching speed and higher current capabilities over more traditional solutions that utilise MOSFETs placed side-by-side.

 [stextbox id=”info”]Pure 3D ICs (stacking in package) are still a point of research in most companies, and the big foundries have just figured out the processes and interposer technology for the same[/stextbox]

Challenges before the industry
First, there is the issue of thermal flux. “Stacking multiple active dies directly on top of each other leads to high concentrations of heat which cannot easily be dissipated,” explains Peckham.

SSI technology places active silicon side-by-side with active silicon on top of passive silicon, thus avoiding the thermal flux issues. While this is workable in MCMs, it is still a daunting issue in true 3D chips. IBM, along with 3M, is working hard to overcome this problem.

Since there are many extra steps involved in manufacturing 3D ICs, the possibility of defects introduced in each step is also high. Yield might be lower than for 2D chips.

Testing of independent dice is relatively tough because of the tight integration between active layers. This introduces further possibility of defects going undetected.

Since 3D TC is a new technology, design is relatively complex, and comparatively fewer tools are available.

Also, there is still no consensus on the methods of design, manufacture, testing and manufacturing of 3D ICs. Plus, there are several integration options—via-last, via-first, via-middle, interposers, direct bonding, etc. Hence there are very few standards governing the 3D IC lifecycle, making it very difficult for all stakeholders.

There is also a bit of confusion about how Internet protocol (IP) will have to be characterised to work effectively in stacked-die configurations.

Are 3D chips in production today?
Some or the other forms of 3D stacking has been in use for many years, especially for stacking memory chips. Irvine Sensors Corporation, for example, has been stacking chips for space electronics for the last 20 years. The company also stacks relatively lowpower chips (often memory) for cell phones and consumer products, where small size is needed. However, past examples have always been simple designs, and not done full justice to the benefits of 3D stacking. More complex designs have so far been tough to implement due to heat dissipation issues, cost of manufacture, interconnect technologies, etc.

Now, after years of research, companies are finally figuring out practical ways to manufacture MCMs and package-on-package designs if not stacking-in-package ICs:
1. Xilinx claims to have utilised SSI technology to create the industry’s largest FPGA (Virtex-7 2000T) with a capacity of two million logic cells, and the world’s first heterogeneous 3D FPGA (Virtex-7 H580T) with high-speed 28Gbps serial transceivers. Both are being sold worldwide and used in applications including ASIC prototyping, storage and high-performance computing systems.

“It has taken many years for Xilinx to combine a number of proven manufacturing techniques used by industry-leading partners to create the complete SSI technology manufacturing process and to bring it to a production-ready state. We have been shipping the devices to many customers around the world for about a year now and in 2012 we started to ship our first heterogeneous devices. SSI technology in 3D devices today makes feasible what would otherwise be impossible in a 2D (monolithic) device. Cost is therefore not the primary driver for these applications today but 3D ICs will inevitably migrate down the cost curve as volumes and experience increase over time,” says Peckham.
2. Texas Instruments’ PowerStack technology is being put into production at its state-of-the-art Clark facility, where many of TI’s analogue products go through assembly, packaging and test. The facility also has the capacity for qualifying QFN.
3. TSMC, which is developing TSV technology (called through-transistor substrate within the company), is likely to start commercial 3D chip production in 2013. Last year, there were some reports about Apple basing its A6 processor on TSMC’s 28nm plus 3D stacking technology, but there has been no official announcement yet. Altera is also a TSMC collaborator.
4. Applied Materials Inc., along with the Institute of Microelectronics in Singapore, has set up an advanced 3D chip packaging facility at a cost of $100 million.
5. Samsung apparently has a good 3D packaging technology for memory chips.
6. GlobalFoundries plans to start production around 2014. Although industry giants like Intel and HMC have the technology to fabricate 3D ICs in-house, they have still not started production.


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