Saturday, September 23, 2023

7nm IC Technology Trends And Challenges (Part 2 of 2)

By V.P. Sampath

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Today, oft-delayed EUV source can generate 80 watts of power. But chipmakers want 250 watts to bring EUV into mass production. It has to show reliability and availability. There are other issues as well. As lines become narrower at each node, the industry faces a growing and problematic issue called line-edge roughness. Basically, line-edge roughness is a deviation on the edge of a line. It is a line-width variation that does not scale with feature size. Meanwhile, as before, lithography is tied to the photomask.

At 7nm, photomask makers may need to prepare for both traditional optical and EUV masks. Optical masks are complex and expensive at 7nm. Because of the increased demand on the process window for the wafer, shapes drawn on masks are becoming smaller. EUV mask shapes are less complex than ArFi (193nm ArF immersion) at those nodes.

But EUV brings other issues on the mask. For example, correction for shadowing and other effects at wafer level has the potential to explode mask data volumes.

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Another example is mid-range correction that becomes necessary for EUV masks because of wider dispersion of electrons during the mask-making process as these hit the multi-layer reflective mask.

Fab flow and variation

Patterning, CMP, deposition, etch and other process steps are challenging at 7nm and 5nm. Future devices would require structures with thin, precise and conformal films. And chipmakers would continue to grapple with structures that consist of only a finite number of atoms. It almost seems like a lot of technologies are all being worked on in parallel.

Manufacturing with yield and having reliable devices would be difficult to do.

With those factors in mind, chipmakers face a sometimes-overlooked challenge, namely, process variation. Variation can be defined as any deviation from intended goal. There are various sources of variation in the fab, including within the die, within the wafer and between one tool chamber and another chamber. Variation control is really dropping down to atomic scale. Gate’s critical dimension uniformity requirements are in angstroms not nanometers.

Selective processes

At current and future nodes, chipmakers would require newfangled technologies called selective deposition and selective removal. Combining novel chemistries with atomic-layer deposition or molecular-layer deposition tools, selective deposition involves a process of depositing materials and films in exact places.

Basically, most of our processing today is done based on line-of-sight capability. But soon, these would begin to tunnel through structures and build structures that you cannot see through from the top. So the industry needs to find a way to do selective deposition. Those techniques are somewhat there, but are not mature enough.

Chipmakers, R&D organisations and universities are all working on selective deposition. Materials must also be removed using a related technology called selective removal or atomic-layer etch. This is a next-generation plasma etch technology that enables layer-by-layer, or atom-by-atom, etching. Atomic layer processing is the norm now for many applications.


In chip production, back-end-of-line is where interconnects are formed within a device. Interconnects and tiny wiring schemes in devices are becoming more compact at each node, thereby causing a resistance-capacitance delay in chips. Back-end-of-line would require new tools and materials. But if you make it taller, you may have more resistance-capacitance.

At 5nm, problems become worse. These occur due to the way wiring is done in the interconnect. It is not just in resistance and capacitance, but in how to wire up the transistor. We are seeing a lot of congestion. For that reason, the industry may need to consider an alternative path. This argument pushes us into doing 3D stacking.

Inspection and metrology

Optical inspection, the workhorse technology in the fab, is struggling to detect defects at 20nm and below. e-beam inspection can find tiny defects, but the technology is slow. Optical inspection tools operate at wavelengths down to 190nm. Seeking to capture more defects, a sub-190nm wavelength technology is used.

In addition, the industry is working on next-generation technology called multi-beam e-beam inspection. But this technology might not be ready until 2020. Exact timing will depend on how quickly the core technology can be scaled in terms of the number of beams and beam current.

Meanwhile, metrology, the science of measuring structures and films, is another concern. Today’s metrology tools are capable of measuring structures in two dimensions, and in three dimensions to some degree. But that is not nearly enough for the complexity of current and future devices. In fact, there is no single metrology system that can measure everything. So chipmakers must use several different metrology tools in the flow.

As the industry moves to 7nm and 5nm, there will be a drastic decline in signal-to-noise ratio of metrology tools. To compensate this uncertainty of measurements from each tool, there would be an even greater need for a multiple metrology approach. This means hybrid metrology is inevitable.


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