Fast-track Evaluation And Prototyping

EFLX DSP cores accelerate signal processing
Fig. 4: EFLX DSP cores accelerate signal processing


EFLX cores allow a single SoC design to adapt to multiple requirements quickly using RTL re-configurability instead of locking in an SoC design with hard-wired logic, or trapping something deeply proprietary for a specific customer. These cores also allow field reconfiguration, which is essential for long-lifecycle devices.

EFLX makes the toolkit available to designers for post-production flexibility. By adding BRAM and DSP block RAM architecture, one can provide exactly the type and amount of memory an application requires. This flexibility is accomplished by inserting BRAM between EFLX logic cores, which tile together to make an array controlling these with otherwise unused inward-facing inter-tile I/Os.

External RAM is mapped and compiled onto the array. EFLX cores can be used to upgrade I/O protocols, change encryption algorithms to improve security, enable elements of software-defined radio or accelerate data centre algorithms like search.

Since EFLX core tiles are independent, these can be spaced apart, leaving room for external RAM integration between tiles. Semiconductor designers would have the ability to quickly upgrade their designs, equipment manufacturers would be able to modify product lines as required and end users would be able to optimise performance of their systems to address their own unique use cases and extend their product lifecycles. EFLX arrays could really help system-level SoC architecture.

Conventional IP model

EFLX supplies a full set of tools for populating the FPGA design. Adding a 2500-LUT core to a design should add only 15 cents to the total manufacturing cost of your device.

Benefits are board complexity, form factor, power consumption and performance. It also eliminates the need for all those external I/Os that would have connected your custom chip to the external FPGA and all PCB traces that would have carried those signals.

Fabric is the key to both performance and scalability. Addition of low-latency memory and signal-processing capabilities significantly increase the range of applications addressed by EFLX embedded FPGA-in-SoC architecture.

EFLX compiler

EFLX compiler with full timing files is available under a simple software-evaluation licence. This would enable you to determine area, performance, architecture and floor planning using EFLX-reconfigurable RTL. If you wish to proceed to design and build an evaluation chip, it would provide a fast-track licence for a single-core EFLX array for US$ 50,000. The licence would include full Verilog model, GDS-II, CDL, integration guidelines, EFLX compiler licence with full timing files and bit-stream generation.

Integration assistance will also be provided. To upgrade an EFLX FPGA, you would need to upgrade its RTL code, run it through Simplify Tool to produce an electronic design interchange format netlist and then use EFLX compiler to reconfigure the internal FPGA on the SoC. For such customers, the company has written its own compiler that allows easy upgrades in the field. The business plan and more-efficient FPGA architecture also reduce the number of metallisation layers to lower cost per gate.


  •  Make input RTL to see resources required, that is, LUTs, DSP blocks and RAM
  •  Configure EFLX array
  •  Select EFLX array size, optional DSP, type and amount of RAM, clocks and I/O configuration to connect EFLX array with the rest of the SoC
  •  Input RTL to see the worst-case path and frequency for target EFLX array/node
  •  Generate bit file that programs EFLX array in the SoC to execute RTL

The basic building block for implementing DSP functions is a pre-adder MAC EFLX logic core that incorporates 40 MACs with 22-bit inputs and 48-bit accumulation. The MACs can be combined for double the precision and pipelined for high throughput. These can also be used as complex-number MACs for certain DSP algorithms.

Trend setters

The three main market segments for EFLX core are networking, wireless/digital front-ends and microcontrollers (MCUs). With the sheer number of I/Os EFLX tile has, it can implement 256b or even 512b busses and put logic on the pins that need it.

Another useful feature of programmable logic is applicable to the wireless side of things, especially digital front-ends. If something changes or a hash/algorithm is blacklisted or cracked, you need not replace the entire device, just update it. In this space a little re-configurability goes a long way.


Application engineers who work on software-defined radio use FPGA fabric to swap among multiple modems on the fly. That is something they cannot accomplish easily with a stand-alone custom chip. In the video business, engineers could drive various display scales and resolutions with a single device by customising the FPGA fabric to match up to various display standards.

If your application requires compute acceleration, FPGA fabric could be reconfigured to implement various custom accelerators. But if your application requires custom hard logic that does not happen to be on those devices, EFLX will allow you to design those same benefits into your custom IC.

Enabling customers to customise and optimise

The big issue is not IP but tool chains, each of which may have a portfolio comprising hundreds and thousands of processor variations. In many cases, these variations involve relatively minor changes like pinouts. Incorporating even a single EFLX-100 core in each MCU could dramatically reduce the number of different MCU options. Also, the ability to customise the MCU’s abilities using programmable fabric may have tremendous implications with regards to implementing versatile nodes for use with the Internet of Things (IoT).

As SoC designs get more complex and masks cost millions of dollars, ICs and systems companies need to make their designs flexible enough to handle broader applications to generate more revenue and improve rate of interest, and to build the capability to upgrade critical RTL blocks to handle evolving standards and customer requirements. This flexibility enables new business models wherein system upgrades offering valuable new capabilities can be offered for a fee, or where one chip can be offered in several versions with different reconfigurable RTLs for different applications and priced to the value of each.

Architects, front-end designers and physical design teams need to become familiar with this new technology for applications from MCU to the IoT to networking and more. Evaluation and prototyping of a single-core EFLX design will give customers the experience and insight to build flexibility into their RTL designs, even if the target application requires a larger EFLX array.

V.P. Sampath is a senior member of IEEE and a member of Institution of Engineers India. He is a regular contributor to national newspapers, IEEE-MAS section, and has published international papers on VLSI and networks


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