A flip flop is an electronic circuit with two stable states that can be used to store binary data. The stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems. Both are used as data storage elements. It is the basic storage element in sequential logic. But first, let’s clarify the difference between a latch and a flip-flop.
Flip flop v/s Latch
The basic difference between a latch and a flip-flop is a gating or clocking mechanism.
In Simple words. Flip Flop is edge-triggered and a latch is level triggered.
Read the full comparison of Flip-Flops v/s latch here
For example, let us talk about SR latch and SR flip-flops. In this circuit when you Set S as active the output Q would be high and Q’ will be Low. This is irrespective of anything else. (This is an active-low circuit so active here means low, but for an active high circuit active would mean high)
A flip-flop, on the other hand, is synchronous and is also known as a gated or clocked SR latch.
In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you give an active clock signal. Otherwise, even if the S or R is active the data will not change. Let’s look at the types of flip-flops to understand better.
SR Flip Flop
There are majorly 4 types of flip-flops, with the most common one being SR flip-flop. This simple flip-flop circuit has a set input (S) and a reset input (R). In this system, when you Set “S” as active the output “Q” would be high and “Q‘” will be low. Once the outputs are established, the wiring of the circuit is maintained until “S” or “R” go high, or power is turned off. As shown above, it is the simplest and easiest to understand. The two outputs, as shown above, are the inverse of each other. The truth table of SR Flip-Flop is highlighted below.
| S | R | Q | Q’ |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | ∞ | ∞ |
JK Flip-flop
Due to the undefined state in the SR flip-flop, another flip-flop is required in electronics. The JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.
The input condition of J=K=1, gives an output inverting the output state. However, the outputs are the same when one tests the circuit practically.
In simple words, If J and K data input are different (i.e. high and low) then the output Q takes the value of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. JK Flip-Flops can function as Set or Reset Flip-flops
| J | K | Q | Q’ |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 |
D Flip Flop
D flip-flop is a better alternative that is very popular with digital electronics. They are commonly used for counters and shift-registers and input synchronisation.
In this, the output can be only changed at the clock edge, and if the input changes at other times, the output will be unaffected.
| Clock | D | Q | Q’ |
| ↓ » 0 | 0 | 0 | 1 |
| ↑ » 1 | 0 | 0 | 1 |
| ↓ » 0 | 1 | 0 | 1 |
| ↑ » 1 | 1 | 1 | 0 |
The change of state of the output is dependent on the rising edge of the clock. The output (Q) is same as the input and can only change at the rising edge of the clock.
T Flip Flop
A T flip-flop is like a JK flip-flop. These are basically a single input version of JK flip-flops. This modified form of JK flip-flop is obtained by connecting both inputs J and K together. It has only one input along with the clock input.
These flip-flops are called T flip-flops because of their ability to complement its state (i.e.) Toggle, hence the name Toggle flip-flop.
| T | Q | Q (t+1) |
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 0 |
Applications of Flip-Flops
These are the various types of flip-flops being used in digital electronic circuits and the applications of Flip-flops are as specified below.
- Counters
- Frequency Dividers
- Shift Registers
- Storage Registers
simple for me to understand good
i think the diagram for SR – flip flop is wrong dude.
No bro
Yeah, the AND gates are supposed to be OR gates. Funny huh
you are wong
they are suppose to be or gates. you are wrong
He is right and so are you. There’s 2 ways to make an S-R latch.
The most common one is using AND gates followed my NOR gates.
The second way is using only NAND gates like he is using above.
the only difference is when we activate S and R at the same time (which is to be avoided)
hi
Shouldn’t the second row second column element of Truth table for T-flip flop be ‘0’ instead of ‘1’? i.e., when T = 1 and Q = 0 the output is 1.
good
well explained
Thank you for your feedback.
your second row of t flip flop is wrong please correct it many student refer your site . So rectify as soon as possible .
Exactly it’s a rs flip flop
what is the correction dude?
Excellent
Hi, I would like to construct a single touch switch using a D flip flop IC, 555 timer, 5v relay module and a capacitive touch pad. So how do i connect the D flip flop to the touch switch circuit for it to work. please i need a reply.
This article needs correction. A D-latch isn’t the same thing as a D Flip flop. See: https://imgur.com/a/NboMq51
It’s good
Thank You for your feedback.
Anyone please clarify what does the author mean by the jargon ‘clock edge’. What does he mean exactly?
Can you give this JK flip flop IC implementation?