Monday, December 22, 2025

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Scaling AI is hitting a wall. New interconnect technology links hundreds of accelerators to work together with reduced latency and higher data flow.

Panmnesia Announces Sample Availability of PCIe 6.4/CXL 3.2 Fabric Switch, The Industry’s First Fabric Switch Silicon Fully Implementing the CXL 3.2 Standard with Port-Based Routing (PBR) Support
Panmnesia Announces Sample Availability of PCIe 6.4/CXL 3.2 Fabric Switch, The Industry’s First Fabric Switch Silicon Fully Implementing the CXL 3.2 Standard with Port-Based Routing (PBR) Support

Data centers and high-performance computing (HPC) environments are struggling to scale AI workloads efficiently. Companies running large AI models such as deep learning recommendation systems, large language models, or retrieval-augmented generation need to link hundreds or thousands of accelerators while keeping latency low and performance high. Current interconnects often require manual configuration, static hierarchies, or slow multi-switch networks, creating bottlenecks and driving up costs.

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Panmnesia’s PCIe 6.4/CXL 3.2 Fabric Switch addresses these challenges. It lets multiple devices operate as a single, large-scale accelerator by supporting port-based routing (PBR) and self-organizing, topology-agnostic fabrics. Devices across racks can connect with minimal latency, reducing the need for complex setup or extra networking hardware. Its hybrid design supports both PCIe Gen 6 and CXL 3.2 on one chip, fully compatible with earlier PCIe and CXL generations.

The switch also improves communication speed within clusters. By enabling PCIe Gen6 speeds and supporting all CXL subprotocols, it ensures cache coherence, faster bulk data transfers, and eliminates redundant data copies. Its high-fan-out architecture and low-latency controller reduce internal processing delays to double-digit nanoseconds, letting accelerators and CPUs work together efficiently.

Beyond the switch, Panmnesia offers standalone PCIe/CXL controllers and custom silicon solutions. These allow customers to build chips optimized for specific workloads such as memory-heavy tasks, accelerator clusters, or CPU-centric designs while maintaining low latency and high throughput. Early access partners are already receiving samples, enabling them to design systems that scale AI and HPC workloads more efficiently and cost effectively.

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“Today, we are excited to unveil our PCIe 6.4/CXL 3.2 Fabric Switch silicon sample,” said Dr. Myoungsoo Jung, CEO of Panmnesia. “We believe that this will be a meaningful milestone in our journey to redefine end-to-end AI infrastructure with our industry partners.”

Nidhi Agarwal
Nidhi Agarwal
Nidhi Agarwal is a Senior Technology Journalist at EFY with a deep interest in embedded systems, development boards and IoT cloud solutions.

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