An analog-to-digital converter that can achieve ultra-high sampling speeds while minimizing footprint and energy consumption, meeting the demands of AI data centres.
Imec has introduced a 7-bit, 175GS/s massively time-interleaved slope-ADC, implemented in 5 nm FinFET technology. The device combines a record-small core area of 250 × 250 µm² with low conversion energy of 2.2 pJ per sample, offering one of the fastest reported sampling speeds. The ADC is designed to support high-throughput wireline interconnects, where precise signal conversion, compactness, and energy efficiency are critical.
The advantages of the design are apparent for optical communication networks, data centres, and other high-speed digital systems. By maintaining wide bandwidth at ultra-high sampling rates, the ADC enables scalable and energy-efficient operation of 2,048-channel time-interleaved arrays, supporting AI workloads, cloud computing, and next-generation networking applications. Its compact footprint helps reduce interconnect lengths and parasitic losses, while low power consumption mitigates thermal and energy constraints in densely packed systems.
Several technical features underpin these capabilities. A patented linearization approach shapes the slope signal to correct distortions, while switched input buffers efficiently drive the massive time-interleaved array without compromising signal integrity. The combination of these techniques allows high-speed sampling beyond 100GS/s without the typical area and energy penalties seen in conventional ADC architectures.
Building on this achievement, the company plans to explore follow-on designs in 3 nm and 14-angstrom nodes to further increase speed and energy efficiency. The research highlights a pathway for compact, low-power converters capable of supporting future wireline systems and ultra-high-speed optical transceivers.
