MIT engineers devise a chip fabrication trick that lets paired electronics authenticate each other securely without storing secret keys externally, a potential leap for secure, low-power embedded systems.
MIT researchers have developed a novel semiconductor processing method that could sharpen hardware-based cryptographic security while cutting reliance on external key storage. The technique embeds a shared, immutable “fingerprint” in paired chips during manufacturing, enabling one device to authenticate its counterpart directly a departure from conventional schemes that typically require secret fingerprint data to be held on servers or third-party systems.
At the heart of the approach is a physical unclonable function (PUF), a unique identifier that emerges from the inevitable microscopic variations in CMOS fabrication. Historically, these random physical signatures have been used to generate device keys, but securing and storing those keys externally introduces vulnerabilities and energy overhead. The MIT team’s process forges a matched PUF pair across two chips by manipulating transistor properties along their shared boundary before the wafer is effectively giving both devices the same hard-to-replicate hardware ID.
This shared PUF lets two devices authenticate one another without ever exchanging or storing secret data beyond silicon. The researchers demonstrated prototype paired chips with over 98 % reliability in matching their unique fingerprints. Because the method uses standard CMOS processes and low-cost LED-induced transistor breakdown to generate correlated randomness, it holds promise for scalable implementation in mainstream electronics.
The innovation could prove valuable in power- and weight-sensitive systems such as ingestible medical sensors paired with wearable monitors where conventional cryptographic protocols and key exchanges are too heavy or slow. By embedding security directly into the hardware, the need for intermediary servers or complex key-management infrastructures can be reduced, improving both efficiency and privacy.
Researchers involved include graduate students Eunseok Lee, Jaehong Jung and Maitreyi Ashok, with senior guidance from professors Anantha Chandrakasan and Ruonan Han. The group presented their findings at the IEEE International Solid-State Circuits Conference, situating the work within broader efforts to strengthen physical-layer security for edge devices.
With rising industry interest in hardware-based cryptographic protections including secure cryptoprocessors and confidential computing architectures that safeguard data in use, this twin-PUF method adds a practical tool for future secure silicon designs.
