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This is your role
- You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDA’s Questa products and services.
- You’ll fosters a climate conducive to help grow customer satisfaction with Siemens’ tools by helping them successfully deploy new flows and methodologies.
- Optionally mentor and manage a team of application engineers, supervise and guide them on the accounts and engagements that they are working on.
- You’ll be working with customers with varying design styles and methodologies to craft the most effective technical solutions.
- You’ll provide key expert advice and contribute to technical campaigns in other regions.
- Identify and qualify potential new business opportunities and work the account teams to build an engagement plan.
- Work with Account Managers and the world-wide teams for forming strategies and driving Siemens’ tools for customer projects to enable business success for Siemens EDA.
- Become a trusted advisor to your customers.Will have moderate travel within India and abroad
We are not looking for superheroes, just super minds
- You’re a Graduate / Postgraduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 3 – 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools.
- You’ve solid understanding on VHDL/Verilog, System Verilog and Assertions.
- Proficient with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification (Clock Domain Crossing – CDC & Reset Domain Crossing – RDC) on designs
- Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is encouraged
- Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products will be an added advantage
- Low power verification techniques using UPF and CPF will be a benefit
- Exposure to static timing analysis (STA) flows involving SDC is a plus