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Location: Bengaluru
Company: AMD
This role focuses on architecture, RTL integration, and silicon-quality implementation of memory BIST, redundancy, and repair solutions across complex SoCs. The engineer will work closely with DFT, PD, DV, firmware, and silicon bring-up teams to ensure robust memory yield, reliability, and test coverage from RTL to production silicon.
Key Responsibilities
- STAR Memory System (SMS) Design Integration & DFX DV
- Architect, integrate, and maintain Synopsys STAR Memory System solutions for embedded memories (SRAM, register files, ROM where applicable)
- Own MBIST, BISR, and redundancy repair flows using STAR controllers, sequencers, and interfaces
- Define and implement memory test architectures, including:
- March algorithms
- Repair analysis and fuse programming
- Power-aware and low-power test modes
- Integrate SMS IP with:
- SoC reset, clock, and power domains
- JTAG / test access mechanisms
- Firmware-controlled repair and status reporting
Preferred Experience
- B.E./B.Tech/M.E./M.Tech in Electronics / Electrical / Computer Engineering
- hands-on experience in silicon design or DFT/DFX-DV/MBIST
- Hands-on experience with Synopsys STAR Memory System
- Deep understanding of:
- Embedded memories (SRAM, RF)
- MBIST, BISR, redundancy, and fuse-based repair
- Memory fault models and March tests
- Strong RTL skills in Verilog/SystemVerilog
- Strong understanding of CPP.
- Understanding of SoC clocking, reset, and power architectures
- knowledge with synthesis, STA awareness, and timing closure support
- Strong debug skills across RTL, GLS, and silicon
Academic Credentials
- Bachelor’s or Master’s degree in Computer Engineering/Electrical Engineering
