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- Design, synthesize and optimize signal processing blocks using C++ for high level synthesis tool, Catapult
- Write MATLAB reference model for verification and performance analysis of the block
- Write module level test benches using C++ with respect to reference models
- Execute module level and system level verification of the processing blocks with functional and code coverage.
- Synthesize C++ model into RTL for ASIC and FPGA libraries using HLS tool with desired PPA
- Able to run RTL synthesis for ASIC/FPGAs for timing closure and performance analysis of the generated RTL
- Write high level and low-level documentations for the blocks
- Work with the application engineering team to understand the design requirements
- Interact with customers to help them with the blocks and to provide solutions
- Master’s/Bachelor’s degree in Electronics and Communication Engineering or equivalent preferred.
- 3-8 years of implementing Signal processing designs and algorithms.
- Strong Knowledge of hardware design and C++
- Knowledge of modelling hardware blocks using MATLAB
- Hands on experience in designing and implementing Digital Signal Processing blocks for Video and/or communication using C++/VHDL/Verilog
- Experience with any HLS tool
- Knowledge of scripting language like Perl/Python/Tcl.
- Excellent documentation, presentation and communications skills.