A new family of high-speed data converters brings advanced digital signal processing directly onto the ADC, cutting system complexity, cost, and FPGA load in demanding signal-chain designs.
A newly launched family of high-speed analog-to-digital converters (ADCs) by Silanna Semiconductor is reshaping signal-chain design by integrating a feature-rich digital signal processor (DSP) directly onto the converter. The move allows engineers to handle key signal-conditioning tasks at the ADC level, reducing reliance on external FPGAs and simplifying overall system architecture.
The DSP-enabled ADCs support resolutions from 12 to 16 bits and sampling rates ranging from 5 MSPS up to 250 MSPS, targeting applications across industrial automation, communications infrastructure, test and measurement, medical electronics, and defense systems. By shifting functions such as decimation and digital down-conversion on-chip, the devices free system resources while improving signal fidelity and lowering total system cost.
The key features are:
- 12- to 16-bit resolution with up to 250 MSPS sampling
- On-chip DSP with decimation and digital down-conversion
- Integrated interleaving and IQ-mismatch correction
- Pipeline ADC core with on-chip reference and clock management
- LVDS and CMOS outputs with SPI-compatible control
Unlike traditional single-purpose converters, the new ADC family is built on a configurable converter core that enables multiple device variants to be factory-defined from a common silicon platform. This approach improves production scalability, shortens lead times, and reduces long-term supply risks, while avoiding end-of-life issues tied to custom configurations.
The integrated DSP performs operations that are typically handled downstream, including channel interleaving and IQ-mismatch correction. Executing these functions at the converter output helps designers optimize usable bandwidth and enhance signal-to-noise ratio (SNR), while reducing calibration effort at the system level.
From a hardware perspective, the ADCs combine a pipeline converter architecture with on-chip reference and clock management, supporting both LVDS and CMOS outputs. Configuration and control are handled through a standard three-wire serial interface, easing integration into existing platforms. Multiple package options, including compact footprints down to 5 × 5 mm, make the devices suitable for space-constrained designs.
With extended temperature options and evaluation kits already available, the new DSP-integrated ADCs are positioned as a practical drop-in solution for next-generation signal chains that demand higher performance with fewer external components.
