- Experience: 10+ Years
- Location: Bengaluru / Hyderabad
- Domain: ASIC | SoC | CPU / GPU
What You’ll Own
- Lead end-to-end Physical Design of complex CPU/GPU Full Chip / Subsystem blocks
- Drive Floorplanning, Placement, CTS, Routing & Signoff
- Own PPA (Power, Performance, Area) targets and closure
- Guide and mentor a team of PD engineers
- Collaborate with RTL, DFT, and Verification teams for seamless tapeout
- Drive timing closure (STA) across multiple corners & modes
- Manage IR drop, EM, and power integrity signoff
- Interface with foundry and EDA tool vendors
What We’re Looking For
- 10+ years of Physical Design experience in ASIC/SoC
- Proven Full Chip PD experience — not just block-level
- Strong CPU and/or GPU design background
- Expertise in advanced nodes — 7nm / 5nm / 3nm
- Proficiency in Cadence Innovus / Synopsys ICC2
- Strong STA skills — PrimeTime / Tempus
- Experience with power analysis — Redhawk / Voltus
- Familiarity with DFT integration & ECO flows
- Scripting: TCL, Python
- Prior lead / tech lead experience preferred
Preferred
- Experience with TSMC / Samsung advanced nodes
- Low-power design (DVFS, power gating, clock gating)
- Exposure to custom / mixed-signal blocks
- Tapeout ownership experience
