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Location: Pune
Company: Lattice Semiconductor
Responsibilities & Skills
Lattice Semiconductor is seeking a STA/Timing Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.
Role Specifics
- This is a full-time individual contributor position located in Pune, India.
- The qualified candidate will be implementing RTL to GDSII flow for complex design.
- The qualified candidate will work on block and full chip timing including timing constraints, analyze timing paths and coverage and timing signoff
- The qualified candidate will work on timing constraints, SDC generation, analyze timing paths, generate timing ECOs for block and full chip and finally complete timing signoff
- The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.
- Collaborate with different cross functional teams including design, DFT, PNR and verification team including providing feedback on timing bottlenecks in design architecture and achieve best performance
- The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.
Accountabilities
- Serve as a key contributor to FPGA design efforts.
- Drive and work on block and full chip timing and bring best-in-class methodologies to achieve best power, performance, and area.
- Ensuring design quality through timing validation quality checks and signoff.
- Develop strong relationships with worldwide teams.
- Mentor and develop strong partners and colleagues.
- Occasional travel as needed.
Required Skills
- BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
- 3+ years of experience in driving backend integration activities of ASIC blocks and full chip.
- Experience on working with industry standard physical design tools including Tempus, Innovus, voltus, Genus, conformal etc.
- Independent worker with demonstrated problem-solving abilities.
- Proven ability to work with multiple groups across different sites and time zones
