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Location: Bengaluru
Company: SanDisk
This role is ideal for a seasoned MSIP methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.
Key Responsibilities
- Mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows.
- Architect and maintainend-to-end custom design methodologies, from transistor-level design through signoff-ready layouts.
- Drivelayout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability.
- Define and enforcephysical verification methodologies, including:
- DRC
- LVS
- PERC
- Reliability and signoff checks
- Own and evolve signoff methodologies for mixed-signal IPs, including EM/IR analysis and reliability verification.
- Work closely with custom circuit designers and layout teams to identify recurring issues and introduce automation, checks, and best practices.
- Collaborate with foundry counterparts to understand process-specific constraints, reliability requirements, and rule interpretations.
- Develop correct-by-construction and shift-left flows to catch issues early and reduce iteration cycles.
- Drivetool qualification, flow robustness, and productivity improvementsacross multiple IP programs.
- Mentor engineers and foster a culture of quality, rigor, and innovation within the CAD/methodology team.
Qualifications
- 3-5years of experiencein mixed-signal / analog design, custom layout, CAD, or methodology roles.
- Strong understanding of transistor-level circuit design, including device behaviour, biasing, matching, noise, and variability.
- Hands-on experience with custom layout design and a deep appreciation of layout quality and its impact on circuit performance.
- Expertise inphysical verification and signoff, including:
- DRC, LVS, PERC
- EM/IR and reliability signoff tools
- Proven experience architecting custom design and verification methodologies for mixed-signal IPs.
- Strong understanding of interactions between circuit design, layout parasitics, and signoff requirements.
- Proficiency in scripting and automation using SVRF, SKILL, TCL, Python, and/or Perl.
- M.Tech / MS in VLSI Design, Microelectronics, or a related field (or equivalent industry experience).
Desirable Skills
- Exposure toadvanced nodesand complex signoff requirements.
- Experience withmemory controllers or high-performance data-path designs.
- Prior experience applyingAI/ML in EDA or design automationis a strong plus.
- Strong communication and stakeholder management skills.
