Tuesday, June 6, 2023

FIFO Design Using Verilog

Presented here is a first-in, first-out (FIFO) design using Verilog that is simulated using ModelSim software. In this article, we design and analyse FIFO using different read and write logics. -- Nidhi Kathuria is a senior application engineer at EFY Tech Center, New Delhi

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Now, click on Zoom Full from Wave window. Your simulation output waveform will be as shown in Fig. 14. Note that, we have already provided 32-bit input values to all 64 address locations. You can check the first data as 32’ h42_41_4C_4C in the first location on this screenshot. By scrolling the cursor towards right, you can see the data in the last location as 32’h41_52_54_49.

Thus, the result of FIFO design is verified from this output waveform.

Future applications

FIFO logic described here can be further refined to make more advanced-level projects. For example, in system on chip designs, there are components that often run on different clocks. So to pass data from one component to another, we need an asynchronous FIFO.

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Sometimes, even if the source and request sides are controlled by the same clock signal, FIFO is needed. This is to match the throughputs of the source to the request. For example, the source may be supplying data at the rate at which the request cannot handle or, in other case, may be placing requests for data at a rate at which source cannot supply. Here, a synchronous FIFO is used that acts as an elastic buffer.

Feel interested? Check out other projects in the circuit section.




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