APPLY HERE
Location: Hyderabad
Company: ApexPlus Technologies
Requirements
- Should be comfortable with Vivado
- Coding language: VHDL/Verilog/SystemVerilog
- Should have developed AXI peripherals for Zynq and other Xilinx FPGAs. Should have a knowledge of the PS and PL parts.
- Should know how to implement timing and other constraints
- Should know how to interface external memory using the EMC in Vivado
- Should know how to write test benches and run simulations
- Should have a working knowledge of Matlab, C & Python
- Should know how to configure Microblaze and run bare metal C code
- Should know how to write PC side code for interfacing over RS232
- Should know how to read schematics
- Should have implemented State Machines
