Apple A20 Pro is among the first smartphone processors built on a 2-nanometre process. Here is what the 2 nm label actually describes, and what changes inside the transistor.
Apple announced the A20 Pro on 9 September 2026 for the iPhone Duo and iPhone 18 Pro. Apple says the processor is built using the latest 2-nanometre process technology. But 2 nm is not a measurement of a transistor. It is a process-generation label that broadly represents advances in transistor density, performance and power efficiency. Modern node names stopped corresponding directly to a single physical feature more than a decade ago. TSMC’s N2 process, for example, uses gate-all-around nanosheet transistors, although Apple has not disclosed the foundry or specific process implementation used for the A20 Pro.
The major architectural change associated with this generation is the move from FinFETs towards gate-all-around (GAA) nanosheet transistors. FinFETs, used in leading-edge processors since the early 2010s, raise the conducting channel as a vertical fin, with the gate surrounding three sides. GAA nanosheets instead use thin horizontal silicon sheets, with the gate surrounding each channel. This provides stronger electrostatic control, helping reduce off-state leakage while maintaining drive current. Nanosheets also allow designers to tune transistor characteristics through sheet dimensions rather than the more discrete fin configurations of FinFETs.
Manufacturing these structures is considerably more demanding. Nanosheet fabrication involves forming alternating silicon and silicon-germanium layers, selectively removing the sacrificial material to release the silicon channels, and then forming the gate dielectric and metal around them. Inner spacers must also isolate the gate from the source and drain in confined three-dimensional regions. Selective etching, channel release and gate formation require tight process control because small variations can affect transistor performance and yield.
Apple reports that the A20 Pro has a 6-core CPU up to 20 per cent faster than the A19 Pro, a 7-core GPU up to 40 per cent faster and more power efficient, and a Dual 16-core Neural Engine with twice the compute performance for on-device AI. It also offers 50 per cent more unified memory bandwidth. The processor uses a new package design inspired by Apple’s M-series chips and connects directly to a next-generation vapour chamber. Apple says the chamber has three times the surface area of the previous generation and enables up to 40 per cent higher sustained performance in the iPhone 18 Pro.
The supply chain is concentrated at this leading edge. TSMC, Samsung Foundry and Intel Foundry are among the companies developing GAA nanosheet processes, but Apple has not confirmed which foundry makes the A20 Pro. TSMC says its N2 process entered volume production in the fourth quarter of 2025. At the equipment level, ASML is the sole supplier of EUV lithography systems, making advanced smartphone processors dependent on a tightly concentrated manufacturing ecosystem.
India assembles iPhones but does not currently fabricate their leading-edge processors. The iPhone Duo starts at ₹299,900 for the 256 GB model in India, with pre-orders opening on 16 October. India’s semiconductor programme is building domestic fabrication, assembly, testing and design capabilities, but the announced fabs do not yet target the leading-edge generation used by processors such as the A20 Pro. The Tata Electronics–PSMC project in Dholera targets 28-nanometre and above technologies, while other projects focus on assembly and testing. For Indian designers, the nearer-term relevance of GAA is therefore through PDKs, EDA tools and access to advanced foundry platforms. The Design Linked Incentive scheme is already supporting domestic semiconductor design.
The next possible step is the complementary FET, or CFET, where n-type and p-type transistors are stacked vertically instead of placed side by side. This could further reduce standard-cell dimensions, but it remains a research and integration challenge. Imec’s roadmap places CFET after further nanosheet and forksheet scaling, making it a longer-term development rather than an immediate successor to today’s 2-nanometre chips.
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