AI agents can assist in chip verification, but specifications, waveform analysis and gate-level debugging still require human involvement.
Artificial intelligence (AI) agents are beginning to automate parts of semiconductor verification, but three tasks remain difficult for current systems to handle reliably. These are creating verification test plans from large specifications, analysing large waveform files and debugging gate-level simulations.
In a recent conversation, Vikash Kumar, senior verification architect at Arm, said these tasks highlight a key limitation of current AI agents in handling large and complex verification context.
This limitation matters because semiconductor verification involves large specifications, complex testbenches, simulation data, and designs containing billions of transistors. While AI agents can automate smaller, well-defined tasks, they cannot yet be trusted to independently handle every stage of verification.
The first challenge is test-plan generation. A verification plan often has to be built from specifications that can span thousands of pages and refer to other specifications. An agent needs to understand this information before it can determine which features, scenarios and corner cases need to be tested. “Test plan is where it’s very hard to give all the context,” Vikash said.
An AI agent can generate a test plan from a specification, but the result may not be reliable if the model cannot process the complete context. Engineers, therefore, need to provide additional information, including the intended verification approach and the areas that must be covered.
This is particularly important because the test plan becomes the basis for subsequent verification work. Errors at this stage can propagate into test generation and coverage.
The second limitation is waveform analysis. Simulation can produce FSTB waveform files that may reach gigabytes in size. Asking an AI agent to trace a signal through such a file and determine what caused a failure can exceed the model’s practical context capacity.
An agent may be able to inspect selected portions of the data or help an engineer investigate a specific signal, but processing an entire complex waveform and reliably identifying the root cause remains difficult.
The third challenge is gate-level simulation (GLS). Unlike register-transfer level (RTL) simulation, GLS works with a netlist containing gates and includes actual timing delays. Tracing a failure through this level of detail requires understanding a large amount of design and simulation context. Vikash said, “GLS debugging remains difficult for current AI systems because of the complexity involved in determining what went wrong.”
These limitations do not prevent AI agents from being useful in semiconductor verification. They can still support engineers with smaller tasks where the problem and required information can be clearly defined.
