See how a new interface IP helps chip designers reduce wiring, cut power use, and support faster data transfer in compact devices.
Silvaco Group has introduced the Mixel MIPI C-PHY/D-PHY Combo Universal IP for TSMC’s N2P 2nm process technology. The IP is designed for semiconductor companies developing chips for devices that require fast data transfer, low power use, and compact designs, such as augmented reality (AR) glasses, wearables, cameras, and mobile devices.
The new physical layer IP supports the MIPI C-PHY v2.1 and MIPI D-PHY v3.6 standards. It is built to reduce power consumption, chip area, leakage current, electromagnetic interference (EMI), and heat generation while maintaining high-speed performance.
One of its key features is support for MIPI D-PHY Embedded Clock Mode (ECM), introduced in the MIPI D-PHY v3.5 specification. This allows data transfer speeds of up to 3.0Gbps per lane using only two wires, compared to the four wires typically required in conventional forwarded-clock D-PHY interfaces. The IP also supports MIPI C-PHY data rates of up to 3.0Gsps per trio, providing an equivalent throughput of 6.84Gbps per trio.
The Universal IP combines both high-speed transmitter and receiver functions and includes full-speed loopback support, allowing designers to use a single IP for different interface configurations.
By using the latest MIPI specifications, the combo IP achieves the same data throughput while reducing the number of required wires by 25% compared to conventional MIPI C-PHY/D-PHY solutions that use forwarded-clock D-PHY. Fewer wires help simplify routing in products with very limited space, such as AR glasses, where interconnects must fit inside thin frames.
The IP is intended for applications where power efficiency and small form factors are important without sacrificing data bandwidth. These include wearable electronics, AR devices, and other compact consumer products.
“We are excited to announce immediate availability of our next-generation MIPI C-PHY/D-PHY IP on TSMC’s N2P process, the advanced Nanosheet technology delivering industry-leading performance and energy efficiency,” said Andy Wright, SVP and GM of Silvaco Semiconductor IP. “This demonstrates our ongoing commitment to expand our portfolio to the leading-edge processes, providing customers with high-performance, reliable solutions for next-generation applications.”
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