A new wave is building in India’s chip design scene, and 1-TOPS is giving students a rare chance to create real, tape-out–ready RISC-V SoCs.
Q.What is the 1-TOPS programme? Can you explain the motivation behind the VLSI Society of India’s launch of the 1-TOPS initiative?
A. The “1-TOPS: 1 Tape-Out Per Student” programme, a unique collaboration between the VLSI Society of India (VSI) and C-DAC, is designed to empower B.Tech and M.Tech students with invaluable industry-ready experience. Through this initiative, students will complete a full chip System-on-Chip (SoC) Tape-Out before graduation.
With an ambitious goal of 100 RISC-V Tape-Outs, 1-TOPS is poised to become the world’s largest student-led SoC Tape-Out programme. Its core mission is to bridge the crucial gap between academia and industry, fostering a new generation of industry-aware and talented engineers for the chip design sector.
Under the 1-TOPS programme, industry experts led student teams will develop RISC-V cores and SoCs, managing the entire process from initial specifications to final Tape-Out, all within a one-year timeframe. These SoCs will be designed and manufactured using advanced process nodes and industry-standard tools and methodologies.
The VLSI Society of India is very thankful to all semiconductor companies for their overwhelming support for the 1-TOPS programme.
Q. Can you provide details on the programme and how students will benefit from it?
A. Under the 1-TOPS programme, students will gain hands-on experience by developing a RISC-V core from scratch and then integrating essential peripheral IPs to create a complete SoC. This initiative goes beyond traditional classroom learning for VLSI Design students, offering a unique opportunity to apply the fundamental concepts learned in their courses to a real-world chip design project and guiding them through every step of the process. Beyond technical expertise, participants will also develop crucial teamwork and soft professional skills vital for success in the workplace, all while working collaboratively towards the ultimate goal of a Tape-Out.
Q. Who can participate in this programme, and what background should participating students have?
A. The 1-TOPS programme welcomes B.Tech and M.Tech students from Electronics and Communication Engineering (ECE), Electronics and VLSI Design (EVD), or any other engineering or science discipline with an interest in VLSI Chip design. The launch of the B.Tech programme in Electronics and VLSI Design (EVD) by AICTE in more than 300 institutes has created massive interest among B.Tech students in the 1-TOPS programme.
Ideally, each 1-TOPS team should be a dynamic blend of students, ranging from second-year B.Tech onwards. While final-year B.Tech and M.Tech students are certainly encouraged to participate, teams must maintain a healthy mix of senior and junior members. This ensures that even as senior students graduate, there remains a robust core of talent to complete the Tape-Out.
Prospective participants should possess a foundational understanding of digital electronics and computer architecture. Most importantly, we are looking for students with solid enthusiasm, strong motivation, and a keen passion to learn all facets of processor and chip design.
Q. What role will the VLSI Society of India play in guiding the students to design a RISC-V core and SoC?
A. The VLSI Society of India and C-DAC are partnering to facilitate 1-TOPS teams in developing their RISC-V cores and SoCs. A cornerstone of this programme is the vital support provided by 1-TOPS coaches – industry volunteers, each bringing over a decade of experience in advanced chip design.
Each 1-TOPS team will benefit from a dedicated 1-TOPS coach who commits 1-2 hours every weekend to guide and facilitate their progress. It is truly inspiring that over 30 highly experienced chip designers from the industry have already volunteered their expertise for this crucial role.
Further elevating the programme, we are honoured to have global RISC-V leaders as our Chief Mentors: Prof. Kamakoti of IIT Madras (renowned for the Shakti Platform) and Prof. Luca Benini of ETH Zurich (known for the Pulp Platform). Their involvement will not only motivate and inspire students but also provide invaluable access to the broader global RISC-V community for support and collaboration.
Q. Which process node are you targeting for the 1-TOPS programme, and how will students access the PDK for the target node?
A. The 1-TOPS programme targets the 65nm or advanced process technology node, leveraging partnerships with leading global fabs such as TSMC, GlobalFoundries, Tower, and the Indian fab of TEPL. The precise node for each project will be collaboratively decided by the 1-TOPS coaches and their respective teams.
The VLSI Society will play a crucial role in supporting teams by facilitating the acquisition of process design kits (PDKs) from these foundries. Additionally, they will provide essential interface IPs (including AXI, AHB, APB, SPI, I2C, UART, and others) critical to the successful development of RISC-V SoCs. We applaud the Ministry of Electronics and IT (MeitY)’s C2S initiative to provide commercial EDA tools from leading vendors to more than 300 institutions, which has helped the VLSI Society of India to conceive the 1-TOPS programme.
Q. MPW manufacturing for 65nm nodes or advanced nodes is expensive. How are you planning to manage the cost of MPW manufacturing?
A. Yes, 65nm or advanced-node manufacturing will involve certain expenses that will depend on die size. We expect that the typical MPW cost for 1-TOPS SoC chips will be approximately 800,000 to 1,000,000 rupees. The VLSI Society is delighted to announce a significant financial commitment covering 50% of each team’s multi-project wafer (MPW) cost, up to 500,000 rupees. Furthermore, the Society will actively support participating institutions in securing the remaining 50% of funding from industry or government, thereby ensuring comprehensive resources for a successful Tape-Out.
Q. Do you have any message for the aspiring students?
A. In response to the pressing demand for seasoned chip design engineers, the 1-TOPS programme is meticulously designed to develop state-of-the-art expertise among students, thereby unlocking remarkable career pathways. This initiative is focused not only on nurturing industry-ready talent but also on solidifying India’s standing as the global epicentre of RISC-V innovation.
