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Location: Bengaluru
Company: Synopsys
You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills—both written and verbal—are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.
What You’ll Be Doing
- Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards.
- Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting.
- Mentoring and guiding junior engineers, fostering growth and technical excellence within the team.
- Estimating project efforts, planning schedules, and executing projects in cross-functional settings.
- Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes.
- Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.
The Impact You Will Have
- Accelerate the integration of advanced silicon IP in SoCs, driving innovation in smart devices and systems.
- Enhance product differentiation and performance, enabling customers to meet demanding market requirements.
- Reduce time-to-market and risk for customers through robust layout design and technical leadership.
- Support Synopsys’ reputation as a leader in DDR & HBM PHY IP development, contributing to industry benchmarks.
- Foster an inclusive and collaborative engineering culture that values accountability and technical excellence.
- Mentor and develop the next generation of layout engineers, ensuring sustained innovation and talent growth.
What You’ll Need
- BTech/MTech in Electronics, Electrical Engineering, or related field.
- 5+ years of relevant experience in layout design, preferably in DDR & HBM PHY IP development.
- Deep understanding of submicron effects, floorplan techniques in CMOS, FinFET, GAA technologies (7nm and below).
- Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.
- Strong ability to lead projects, manage schedules, and ensure product quality within tight timelines.
- Excellent written, verbal communication, and interpersonal skills.
Who You Are
- Innovative thinker with a proactive approach to problem-solving.
- Effective communicator and collaborator across diverse teams.
- Detail-oriented, accountable, and committed to high standards of quality.
- Mentor and leader, fostering growth and technical excellence.
- Adaptable, eager to learn, and open to new ideas and technologies.
- Champion for inclusion, diversity, and teamwork.
