Yosys: Your Solution for Verilog RTL Synthesis

By Priya Ravindran


To map to the library, use command abc [options] [selection]. This invokes ABC, a software system that synthesises and verifies your logic design using scalable optimisation techniques. ABC then maps the internal gate library of Yosys to the target architecture. To validate the logic formula in the design, Yosys takes help from MiniSat, the SAT-solver library.


The Yosys flows

You are free to choose the best format for your design and allow data to flow from input to output in a sequence. The main difference between these flows would be the mapping to library cells. A straight-forward application-specific integrated circuit (ASIC) design is mapped to simple CMOS cells. When synthesising for field programmable gate array (FGPA) based designs, the design has to be mapped to look-up tables (LUTs) that are stored in the library.

Yosys interconnects to Xilinx library to allow for your FPGA to be designed. For logic mapping to digital signal processing (DSP) cells in FPGAs, or synthesis for custom coarse-grain reconfigurable hardware, you can choose to go with the coarse-grain architecture. These cells operate on bit-vectors, instead of single-bit signals, and accelerate the process.

Check for correctness

verilog rtl
Fig. 3: Coarse-grain netlist

As soon as you install your tool, check if it is functioning right. Yosys-bigsim on GitHub provides a variety of real-world Verilog designs and test benches.

VlogHammer is used to check the correctness of the Verilog front-end of Yosys. This currently tests combinatorial circuits described by Verilog expressions by comparing the results from Yosys with other synthesis-tool results, while at the same time also cross-verifying using various simulation engines.

Coming to the verification of your design, a symbolic model check (SMC) formally checks the properties of your circuit. To check if two circuits function identically, you may reproduce a circuit. You may also check the design at two different stages of tool processing, to perform a formal equivalence check. You can also check if a module conforms to interface standards.

What more would you like

Using Emscripten, an exclusive JavaScript port is being developed for Yosys. Called YosysJS, it is meant for building Web applications for educational purposes. When you contrast Yosys with proprietary tools, the main drawback is advanced-level synthesis for timing, power and such factors. May be future releases could see a tweak in Yosys that would cater to these features and much more. Stay tuned to its website www.clifford.at/yosys for regular updates.

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