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Rambus, a premier chip and silicon IP provider, is seeking highly skilled Design Verification Engineer to lead our PCIe/ CXL (Compute Express Link) IP verification efforts. As the CXL IP Lead, you will be responsible for leading a team of verification engineers to ensure that our CXL IP meets the highest standards of quality and performance. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
- Lead the CXL IP verification effort, including defining the verification strategy, developing test plans, and executing tests.
- Manage a team of verification engineers, providing technical guidance and mentoring as needed.
- Work closely with the design team to ensure that the design meets the requirements and is testable.
- Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency.
- Provide regular updates to management on the status of the CXL IP verification effort.
- Bachelor’s or Master’s degree in Electronics Engineering or a related field
- 4+ years of experience in design verification, with a focus on complex IP blocks.
- Strong understanding of PCIe/ CXL protocol and the associated verification challenges.
- Experience leading verification teams and driving verification projects to successful completion.
- Experience with industry-standard verification methodologies, such as SV/UVM.
- Strong problem-solving skills and the ability to debug complex issues.
- Excellent communication skills and the ability to work effectively in a team environment.
- If you have a passion for designing and verifying cutting-edge technology and want to lead the verification effort for our CXL IP, we would love to hear from you