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Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior Member Technical Staff for our IP cores team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
The candidate will be reporting to Selvakumar, Manager Design implementation and is a Fulltime position. The candidate will have a higher exposure to the management and he/she will be part of major technical decision making. The design requires out of box thinking to meet tighter PPA.
- Lead complete ownership of IP cores PHY and Testchip implementation.
- Take complete ownership for Block and SOC implementation depending on the complexity.
- Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 7nm nodes or below.
- Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
- Well versed with IP development and integration process at testchip or SOC level
- Well versed with the timing closure (STA), timing closure methodologies.
- Should be able to provide clear directions to the team on PnR flows.
- Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
- Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification
- Good communication skill to negotiate with top level for convergence.
- Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management.
- Participate in Mentoring new joiners in the group on technical skills.
- Provide inputs for CAD/DA team from Design Implementation perspective.
- Work closely with DFT team on scan aspects and provide inputs from physical design.
- Continuously work on methodology and productivity improvements.
- Must have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
- Must have at least experience in the range of 3 to 5 yrs in physical design
- Must have implemented and completed a minimum of 5 design tapeouts.
- Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
- Experience in Tcl/Tk, PERL is a Plus
- Synthesis experience and exposure besides chip implementation flows is an added advantage
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