Monday, June 24, 2024

Signal Integrity and Power Delivery Engineer At Intel In Bengaluru

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Location: Bengaluru

Company: Intel

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers’ unique product needs. With the first “Open System Foundry” model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel’s secure, resilient, and sustainable source of supply.

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In this role, you will be part of a world-class Silicon design enablement team of highly talented engineers working on Signal and Power Integrity who will take up significant technical role and be expert in one or more technical fields. Enable Signal and Power Integrity solutions for standard and custom designed serial / parallel I/Os. 3D and 2.5D modelling in HFSS, simulations in ADS, Cadence PowerSI, PowerDC, OptimizePI, or equivalent Ansys Tools like Redhawk, Totem, SIwave. Provides solution for Signal and power integrity on die, package and board which affects performance and power of serial and parallel interfaces, such as PCIE4/5/6, TypeC, USB and DDR4/DDR5 memories. Hands on Signal and Power Integrity design, frequency and time domain analysis, Simulations, System modelling, I/O modelling and measurements
In this position, you will be responsible for providing Silicon, package (including 3d, 2.5d, 2d pkg technology) and platform Power and Signal integrity solutions and working closely with design teams for implementation.

Your responsibilities will include but not be limited to:

  • Understands different IP electrical requirements and performs comprehensive simulations and validations to generate Intel design guidelines to guide system-level signal and power integrity design including, but not limited to, Silicon, package, socket, boards, and voltage regulators.
  • Performs DC, AC and transient simulation to provide noise, impedance profile of the whole power delivery path and link/electrical simulations to validate I/O performance from platform to silicon.
  • Perform time domain analysis in HSPICE, ADS to find noise levels in I/O rails.
  • Provides guidance, solution space on implementation with the design team ( IP, SOC, Package and board).
  • Modelling and delivering IP SI and PI collaterals (AMI- IBIS, Die Models, ICCt, Integration guide etc..) for delivering to internal and external customer.
  • Correlating simulations with system measurements.
  • Deliver optimized SI and PI solution meeting the product performance
  • Provides DC and resistance simulation to provide Rpath from the VR to the package pins, voltage drop, current density and power loss analysis.
  • Performs transfer impedance simulations to provide plane split and isolation guidance between interfaces on board package area.
  • Interface with customers and in-house IP, SOC and platform teams to provide the solution to meet the Specification.


  • Candidate must possess a bachelor’s degree or Master’s in Electrical or Electronic Engineering.
  • 3 – 12 years of experience in Silicon, package and board level power integrity design.
  • Solid understanding of theory on power and signal integrity as well as having applied it to actual designs in the industry or in the academy.
  • Knowledge and understanding of how power and signal integrity on die, package, and board affect bit error rate of serial and parallel interfaces, such as high-speed serial channels (i.e., 56G/112G PAM4 and beyond, PCIe Gen4/5/6, etc.) and DDR4/DDR5 memories.
  • Deeper understanding of cross domains like Package, System, Silicon engineering, IO Protocols is an added advantage.
  • SIPI simulation software use such as Sigrity PowerSI, PowerDC, HSpice and Matlab.
  • Package/board routing CAD tools such as Cadence Allegro and Mentor Graphics.
  • Hands-on experience with lab equipment for correlation
  • Working knowledge of board-level system architecture, basic silicon design and package
  • Knowledge in PCB layout process and methodology.
  • Ability to clearly communicate routing rules to layout designers and work with them for successful project release.
  • Ability to communicate effectively across multiple disciplines, such as silicon design, package design, board design, PCB layout, and mechanical design.
  • Great team player, willing to learn and flexible.
  • Solid verbal and written communication skills are required.
  • Ability to work effectively in a dynamic team environment.
  • Familiarity with 3D EM tools like HFSS, Clarity, CST etc is needed
  • Working knowledge of statistical analysis like DOE will be an added advantage.


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