The design uses time-interleaved ADCs with phase tuning and low-jitter clocks to increase sampling rate and signal accuracy in high-speed data systems.
TIDA-01028, the reference design from Texas Instruments (TI) demonstrates how to use two ADC12DJ3200 RF-sampling ADCs in a time-interleaved setup to achieve a 12.8-GSPS sampling rate. The system uses the Noiseless Aperture Delay Adjustment (tAD Adjust) feature to fine-tune the phase between the ADCs and reduce typical mismatches.
The analog front end (AFE) and system clocking architecture are shared across both high-performance digital storage oscilloscopes (DSOs) and wideband digitizers (DAQs). The design includes a flexible analog input path that supports signals from either a transformer or amplifier chain, selected using hardware jumpers. All channels are matched in path delay and clock routing.
To meet the demands of modern signal acquisition systems, the design supports analog bandwidths from 200 MHz to 5 GHz and sample rates ranging from 5 GSPS to several hundred GSPS. Most DSOs still operate at 8-bit resolution, but this design is built to support up to 16-bit resolution for better signal detail.
Time-interleaving allows the system to scale up sampling rates without needing ultra-high-speed, single-core ADCs. Each ADC samples in a fixed sequence, and their outputs are combined to achieve higher throughput. With proper calibration of offset, gain, and phase, the system can reduce interleaving errors and maintain high signal fidelity.
The use of tAD Adjust enables accurate phase control between interleaved ADCs. This helps minimize spurious signals and improves core performance metrics like signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB).
The low-jitter clocking solution ensures that timing noise is kept to a minimum, which directly impacts overall data quality. The JESD204B interface also allows reliable high-speed communication between ADCs and the processing system.
The design’s modular analog input path allows easier testing and validation of system behavior under different conditions. Matching the analog path and clock routing across all channels ensures consistent performance and reduced channel skew.
For DSO users, this design offers the ability to capture clean waveforms with better resolution and dynamic range, making it suitable for debugging high-speed digital circuits, analyzing serial protocols, or testing RF signals.
For digitizer applications, the high resolution and wide dynamic range make it ideal for frequency-domain analysis, where precision matters more than real-time display. Since data is transferred to a host controller for processing, the system also supports advanced post-processing workflows.
In automated test equipment (ATE) and multi-channel setups, this design supports scalable data acquisition with reduced errors, lower cost per channel, and consistent performance across inputs.
By addressing key challenges in clock jitter, interleaving mismatch, and analog signal path design, this system improves signal quality, measurement accuracy, and overall reliability—critical for applications in aerospace, defense, communications, and high-speed electronics testing.
TI has tested this reference design. It comes with a bill of materials (BOM), schematics, assembly drawing, printed circuit board (PCB) layout, and more. The company’s website has additional data about the reference design. To read more about this reference design, click here.
