Saturday, December 10, 2022

Handling 20nm Design Challenges

While the world is working on 22nm manufacturing process, plans are underway for 20 nm and beyond. At 20 nm, there are various issues to deal with, such as complex double-patterning lithography requirements, in-design physical verification throughout the flow, accurate higher levels of extraction and timing analysis to allow for manufacturing variability, and so on. How is the global semiconductor industry handling these and a host of other issues? Find out -- Pradeep Chakraborty

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The Standard Parasitic Exchange Format (SPEF) file produced by extraction tools has been extended to support extraction of multiple parasitic capacitances. The new M-SPEF format provides the capability to capture minimum and maximum values, in addition to the extracted nominal parasitic capacitance extracted at each PVT corner. StarRC has been enhanced to support the multi-value SPEF and also the new format, and has been certified for 20 nm. The information for modeling this variability effect is provided in source technology files with StarRC producing these.

4. Capacity, performance requirements
There are certain performance and capacity requirements for next-generation designs.

According to Ahuja, 20nm ICs may have 8-12 billion transistors. Advanced node technology thus requires performance, power and capacity breakthroughs that should allow electronics OEMs to provide next-generation designs. To meet time-to-market and PPA (performance, power and area) goals for extremely large and fast chips, design productivity must improve multi-fold.

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Faster tools are part of the solution. For example, GigaOpt technology in Encounter toolset provides optimisation across the IC physical design flow, runs on multi-core computers and delivers a 30 per cent run-time speedup on a single CPU.

The other part of the solution is to move up in abstraction level. This is where Encounter GigaFlex technology comes in. It allows designers to model only what they need at high abstraction levels, and add details as the design proceeds and more accuracy is required.

Biddle shares, “We are already seeing Synopsys’ Galaxy Implementation Platform being deployed on designs with over a hundred million gates in addition to billions of transistors for memory. We also see chips designed to perform at greater than 2 GHz. At these chip sizes and performances, leakage power and active power management continue to be a challenge as designers try to harness the performance capabilities of 20 nm while still meeting their power budgets.”

The author was executive editor at EFY till recently



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