These modules should be used as primitive instantiation in the custom RTL so that these get connected to user logic. In some cases, DDR2/3 cores are also specific to some banks of FPGAs.
• Portable across FPGAs, independent of target technology/vendor
• Available as open source IP
• Easy to modify and implement as per custom applications
• Complete data sheet/documentation available for originally-targeted device/technology
• IP cost may be high when compared to firm IP core since source code provided by third party
• Individual IP core licence may be required
• Performance/timing may vary with originally-targeted device/technology
• Documentation might be generic or specific to originally-targeted device/technology
• Support may not be available (or limited support available) for custom modifications
• Extra effort required while targeting custom technology/device
• In-depth understanding of design required before modifications can be made
Several factors must be considered while selecting the suitable IP such as cost of IP, effort required for customisation (for soft IP core), time to market, FPGA family, availability of simulation environment (unit and integrated levels) of IP, documentation, board-level evaluation of IP and support during development, among others. Nowadays, since most basic IP cores come with FPGA implementation tools for free, it makes time-to-market faster and results in lower costs.
In this article, we have taken Xilinx and Altera as examples. But you can find other vendors as per your FPGA designs. So depending on complexity, timeline and overall project cost, you can choose proper IP core type.