New Experimentally Validated Device Models Can Improve Circuit Performance

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Researchers from the IITB and Imec developed a mathematical model to capture manufacturing variations in the device and validated it experimentally.

Today’s electronic devices consist of millions of transistors on a single chip. This trend is fueled by a steady decrease in dimensions of the elements like transistors. Currently we are capable of making MOSFETs with lengths as small as a few nanometers. The Taiwanese manufacturer TSMC currently makes chips with the smallest feature of the circuit measuring just 7 nanometers. The process of fabricating such small elements is complex and despite using the most sophisticated technologies, there are some tiny variations in dimensions and characteristics. Therefore, each transistor is slightly different from another across chips and even on the same chip. For creating optimized solutions, circuit designers must take into account such variations to ensure that each of the billions of chips produced works as expected. Therefore, the need arises for a model that can capture the nanoscale variations introduced during the manufacturing process.

In commercially used simulation software, the device characteristics are inexactly predicted based on simple variation in electrical properties of the transistor. Dr Amita Rawat and Prof Udayan Ganguly from the Department of Electrical Engineering, Indian Institute of Technology, Bombay (IIT Bombay), in collaboration with researchers from IMEC, Leuven, Belgium, have earlier proposed a method to estimate the performance of electronic circuits based on nanoscale manufacturing variations. They have now experimentally validated their earlier proposed method 

The researchers created a mathematical model that accurately captures the behaviour produced by the variations in the transistor electrical properties based on the changes in the physical parameters, such as fluctuations of the pattern lines or metal nanocrystal orientation. They used this mathematical data to create a ‘variability- aware’ transistor model to be used in a commercial design and simulation software. The newly developed model makes it possible to design better-performing circuits.

MOSFETs are the building blocks of major electronic circuits available today. The researchers studied MOSFETs extensively. They drew patterns using UV light on semiconductor chips to mark the channel, gate, interconnects, and other circuit components. They found that the gate metal has nanoscale crystals that are not oriented uniformly in the same direction leading to different atomic interfaces between metal crystal and gate insulator. Such physical variations can significantly affect the device characteristics and overall circuit performance. 

“Our team developed the theoretical modelling of variability over nine years and three PhD theses. The journey is chronicled in a magazine article in IEEE Nanotechnology Magazine. Now our work has reached the experimental validation phase,” says Prof Ganguly. 

The researchers predicted the physical variations for the 14nm technology process using the mathematical model proposed. They compared the data with experimental variations and they found that the worst and best case errors were within acceptable limits. The researchers are now planning to provide this framework as a technology package to be plugged into the circuit design software.

Published work: https://doi.org/10.1109/TED.2021.3053185


 

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