By stacking active devices above existing circuitry, the platform reduces data transfer energy while increasing integration density and performance.
Growing computational workloads are increasing energy losses caused by constant data transfer between logic and memory in conventional microelectronic architectures. As device scaling slows, reducing interconnect energy and improving integration density have become critical for sustaining performance and efficiency gains.
Researchers at MIT have developed a fabrication approach that stacks multiple active components on the back end of a semiconductor chip. The method integrates logic and memory elements into a compact vertical structure, reducing data movement and lowering energy consumption while increasing computational speed.
The approach uses amorphous indium oxide as the channel material for back end transistors, enabling deposition at approximately 150 degrees Celsius without damaging front end circuitry. Precise control of oxygen vacancies in an ultra thin layer around 2 nanometres thick allows stable transistor operation with low switching energy. The platform also integrates ferroelectric hafnium zirconium oxide to form memory transistors roughly 20 nanometres in size, achieving switching speeds of about 10 nanoseconds at reduced operating voltage.
Key features of the research include:
- Back end integration of logic and memory components
- Amorphous indium oxide channel material for low temperature fabrication
- Ultra thin transistor channels with controlled defect density
- Integrated ferroelectric hafnium zirconium oxide memory layer
- Switching speeds around 10 nanoseconds with low voltage operation
Yanjie Shao, lead author of the work, says, “We have to minimize the amount of energy we use for AI and other data centric computation in the future because it is simply not sustainable. We will need new technology like this integration platform to continue that progress.”
