The on-chip all-optical supernode could improve multi-chip AI communication with lower latency, higher energy efficiency and faster distributed AI inference.
The scientists at Peking University have designed an on-chip all-optical supernode that is designed to address bottlenecks in bandwidth, latency, and energy efficiency in multiple-chip AI computing systems. Published in National Science Review (NSR), the optoelectronic distributed computing system utilises a 400 Gbps silicon photonic transceiver chip together with a non-blocking 16×16 optical switch chip, making it possible to route the data in a physical layer with a total aggregate switching bandwidth of up to 6.4 Tbps.
The optical switch chip has been designed with a loss of less than 5 dB, inclusive of coupling loss, which makes it possible to achieve high-speed and error-free transmission of data without requiring external optical gain compensation. In addition to this, it has been designed in a way to offer error-free transmission over multiple paths of switching while maintaining a flat spectral response over a spectral range exceeding 100 nm.
For the demonstration of the system, a five-layer convolutional neural network was used for the task of image denoising, in which different network layers were mapped on different processing nodes using the all-optical network. The intermediate feature maps were sent between processing nodes directly without retransmission and without repeated compute-memory transfers, resulting in the creation of a pipelined parallel computing system that avoids repeated compute-memory communication and helps alleviate the memory-wall problem. In comparison with an established baseline using a GPU to perform the same task, the system is able to achieve more than a hundred-fold increase in inference speed while using only one-ninth of the computing resources.
The team believes that this work could lay the foundation for future large-scale intelligent distributed computing enabled by co-packaged optics, increasing silicon photonic transceiver speeds and AI chips I/O rates.
