Can AI chip development become faster and less complex? A modular chiplet approach aims to simplify custom silicon design.
TYLsemi has introduced a production-ready chiplet portfolio and a custom silicon platform designed to simplify the development of AI infrastructure processors. The offering combines reusable connectivity, power delivery and memory chiplets with an end-to-end silicon integration platform, enabling customers to develop multi-die AI systems using industry-standard interfaces and advanced packaging technologies.
The launch comes as AI infrastructure transitions from large monolithic chips to modular, chiplet-based architectures. As AI accelerators demand higher bandwidth, improved power efficiency and greater scalability, conventional chip designs are approaching physical and manufacturing limits. By providing pre-validated silicon building blocks, TYLsemi aims to reduce design complexity, shorten development cycles and lower the engineering risks associated with building custom AI processors for hyperscalers, cloud providers and system developers.
The portfolio comprises TYL.IO, a family of connectivity chiplets supporting PCIe, ESUN and UALink interfaces, with a roadmap for co-packaged optics (CPO) to enable next-generation rack-scale AI fabrics. TYL.Power is an integrated voltage regulator (IVR) chiplet that delivers intelligent in-package power management to improve system-level power efficiency for AI accelerators.
The company, currently on the product roadmap, will provide memory connectivity for advanced AI systems, with further details to be announced later. These products are complemented by TYL.Forge, a chiplet-enabled custom silicon platform that combines the company’s connectivity and power chiplets with IP, foundry, packaging and manufacturing services to implement customer-defined XPU, compute and fabric designs.
The chiplets support the UCIe die-to-die interconnect standard, allowing compatibility with modern semiconductor packaging technologies and modular silicon integration. Samples of TYL.IO and TYL.Power are expected to be available to qualified customers in 2027 through TSMC, while the company is already engaging lead customers for the TYL.Forge platform.
“At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio,” says Mohit Gupta, Founder and Chief Executive Officer of TYLsemi. “TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging and integration, giving customers a fast, proven path to AI-era silicon.”
Click here for the official announcement.
