An annealing processor architecture that scales both capacity and precision—enabling high-accuracy solutions for complex combinatorial optimization problems in real-world applications.
A research team led by Professor Takayuki Kawahara of the Tokyo University of Science has unveiled a Dual Scalable Annealing Processing System (DSAPS) designed to solve combinatorial optimization problems (COPs) with significantly greater precision and scalability than current approaches. COPs—critical in applications like shift scheduling, logistics, and drug design—are notoriously hard to solve efficiently using traditional computing. Annealing processors (APs), based on the Ising model, offer a promising hardware solution by representing problem variables as spins and minimizing system energy to find optimal configurations.
While fully-coupled Ising models are favored for their ability to directly map any COP without transformation, they suffer from limited capacity (spin count) and precision (interaction bit width). Previous ASIC-based implementations scaled capacity but locked bit width, restricting their ability to tackle problems requiring high numerical resolution.
DSAPS addresses both issues simultaneously through a unique architecture. It incorporates two scalable structures for energy computation blocks (∆E blocks), which function as large-scale integrated (LSI) chips on a CMOS-based AP board.
- The high-capacity structure subdivides each ∆E block into smaller sub-blocks, increasing the number of spins without major hardware changes.
- The high-precision structure processes the same spin interactions across multiple ∆E blocks at different bit levels. Their results are then combined using bit shifts via an FPGA-based control block, multiplying the effective interaction bit width.
In practical tests, DSAPS demonstrated impressive flexibility. One configuration supported 2,048 spins with 10-bit interactions; another handled 1,024 spins with 37-bit interactions—far exceeding typical ASIC designs limited to 4–8 bits.
Validation on MAX-CUT and 0-1 knapsack problems showed that higher bit precision dramatically improves solution accuracy, underscoring the importance of tailoring DSAPS setups to the problem.
“This system enables real-world COPs to be tackled efficiently, with broader implications for scalable, high-precision Ising machines,” said Prof. Kawahara. DSAPS will also be integrated into undergraduate semiconductor design labs starting in 2025.
