Monday, April 22, 2024

New USB 2.0 Type-C IP Cuts Power and Area for IoT Edge Applications

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Synopsys, Inc. today announced it has reduced the power and area of its DesignWare USB 2.0 Type-C Controller and PHY IP for cost-sensitive and energy-efficient Internet of Things (IoT) edge applications targeting 40-nanometer (nm) and 55-nm ultra-low power processes. The IP cuts silicon area by up to 50 percent compared to competitive offerings, saving on average $0.03 per die. To extend battery life, the USB IP uses 30 percent lower active power compared to competing solutions and near 0 W of standby power. The DesignWare USB 2.0 Type-C IP supports the IEEE 1801 standard Unified Power Format (UPF) to speed implementation and testing of power domains. In addition, Synopsys has simplified configuration options in the IP to reduce integration and verification effort by weeks or months.

The DesignWare USB 2.0 Type-C Host, Device and Dual-Role Device Controllers and PHYs are based on Synopsys USB 2.0 IP that has been certified more than 90 times and integrated in thousands of SoC designs shipping in billions of chips. The new DesignWare USB solution supports the USB Battery Charging v1.2 specification, delivering up to 1.5 A of current to IoT devices connected to a wall charger. In addition, the DesignWare USB 2.0 Type-C IP supports advanced power management features, such as power supply gating and support for near 0 W standby current, to help designers reduce leakage for IoT devices. For the fastest, most efficient IC development, the IP eliminates the 80 percent of standard USB 2.0 configuration options that are not essential to IoT systems. In addition to the DesignWare USB 2.0 Type-C Controllers and PHYs, Synopsys offers IP prototyping kits, IP software development kits and verification IP to enable early software development, reduce IP integration risk and speed time-to-market.


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  • DesignWare USB 2.0 Type-C solution, including controllers and PHYs, reduces USB silicon area by up to 50 percent on ultra-low power 40-nm and 55-nm processes
  • Extends battery life with near 0 W standby power consumption and up to 30 percent lower active power
  • Saves months of implementation and verification effort with simplified configuration options



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