Friday, February 13, 2026
HomeElectronics NewsSolving Gate Leakage In GaN Devices

Solving Gate Leakage In GaN Devices

A gate design cuts leakage, raises threshold voltage, and improves stability in GaN power devices, clearing a barrier to wider use in power systems.

Mayank Shrivastava (third from right) holding a representative power device 8” wafer, with some of his PhD students who work on various aspects of GaN Power and RF technology, in ESE, IISc (Credit: Mayank Shrivastava)
Mayank Shrivastava (third from right) holding a representative power device 8” wafer, with some of his PhD students who work on various aspects of GaN Power and RF technology, in ESE, IISc (Credit: Mayank Shrivastava)

GaN devices can reduce energy losses and shrink the size of power converters and other power modules by up to three times, but their adoption has been limited due to constraints in the gate structure that controls current flow. In commercial transistors with a p-GaN gate, the device turns on at a threshold voltage of around 1.5–2 V and may start leaking current when the gate voltage exceeds 5–6 V. A clear understanding of how the gate governs transistor behaviour and determines the threshold voltage has been missing.

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Researchers at the Indian Institute of Science (IISc) have identified design principles for gallium nitride (GaN) power transistors, helping make them safer and easier to use in systems such as electric vehicles and data centres.

In the first phase, the team developed gate variants and linked electrical measurements with modelling and microscopy. They found that device behaviour depends on whether the p-GaN layer is fully or partially depleted. In the partially depleted state, leakage paths play a key role. If positive charge builds up at a critical interface, the device turns on early. If this charge build-up is suppressed, depletion extends first and the transistor switches on later, at a higher threshold voltage. Shrivastava says small leakage paths can decide the turn-on behaviour.

Based on these findings, the team designed and demonstrated metal-based gate stacks that reduce gate leakage by up to 10,000 times. These designs also improve threshold stability and achieve gate breakdown voltages of around 15.5 V.

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In the second phase, the researchers converted these insights into an aluminium–titanium oxide (AlTiO)-based p-GaN gate stack. This patented structure suppresses charge injection and enforces a high-threshold depletion-extension mode. The devices achieve a threshold voltage above 4 V, close to silicon MOSFET levels, while maintaining gate control, threshold stability, and gate breakdown voltage.

These results can enable wider use of GaN in applications where reliability and performance margins matter, while also opening opportunities for indigenous development of power electronics solutions. The team is now focused on scaling the technology for commercial deployment through government support, industry licensing, and partnerships.

Nidhi Agarwal
Nidhi Agarwal
Nidhi Agarwal is a Senior Technology Journalist at EFY with a deep interest in embedded systems, development boards and IoT cloud solutions.

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