A Look At The New RISC-V Specifications Of 2022

By Aaryaa Padhyegurjar

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The global open-design standards pioneer, RISC-V International, has announced the first four specification and extension approvals for 2022. The announcement builds on the pace RISC-V had established in 2021, when 16 standards covering more than 40 extensions were ratified.

“The RISC-V culture of contribution and collaboration continues to produce impressive and strategic results,” said Calista Redmond, CEO of RISC-V. “RISC-V members are leaders in the era of open compute, proving that collaboration accelerates innovation through shared investment while growing global opportunity.”

“These new specifications accelerate embedded and large-system design,” said Mark Himelstein, CTO of RISC-V. The new specifications are as follows:

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1] Efficient Trace for RISC-V (E-Trace)

  • E-Trace for RISC-V provides a branch trace-based approach to processor tracing that is suited for debugging a wide range of applications, from small embedded designs to supercomputers.
  • The signals between the RISC-V core and the encoder (or ingress port) are specified in the documentation, along with a compressed branch trace method and a packet format to encapsulate compressed branch trace information.

2] RISC-V Supervisor Binary Interface (SBI)

  • Using an application binary interface in supervisor mode (S-mode or VS-mode), the RISC-V standard for SBI creates a firmware layer between the hardware platform and the operating system kernel. This abstraction allows all RISC-V operating system implementations to share platform services.
  • Because many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, ratifying it would enable a consistent approach across the whole RISC-V ecosystem, assuring compatibility.

3] RISC-V Unified Extensible Firmware Interface (UEFI) specifications

  • UEFI is an important component of any system. It may be able to take the place of simple BIOS software in some cases.
  • Existing UEFI standards are brought to RISC-V processors via RISC-V UEFI Protocols.

4] RISC-V Zmmul multiply-only extension

  • Division operations are too uncommon in many microcontroller applications to justify the cost of divider hardware. Simple FPGA soft cores will benefit from the RISC-V Zmmul expansion in particular.
  • It enables low-cost implementations that require multiplication operations but not division.





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