The complex chip is equipped with billions of transistors and has been developed by engineering teams across the globe
With a team of up to 200 engineers working to design a 500 square millimetre chip having over 30 billion transistors, 40 million flipflops and 23 thousand pads for I/O, power and ground, Sondrel has announced the completion of the final-phase for its largest chip design.
Around a third of the chip has been assigned to the block that handles real-time image processing. The chip also supports blocks of Graphical Processor Unit, two Central Processor Units, on-chip cache memory, PCI and USB interfaces plus memory controllers to off-chip memory using over 7 kilometres of metal tracks on a chip the size of a postage stamp.
Designing a chip of this complexity in one go would have been impossible as it has 300 million placeable logic cells and the placement tool can only handle 3 million at a time without the runtime becoming excessive. It was therefore divided into manageable-sized, functional blocks over four levels of a hierarchy structured like a pyramid. This enabled the designing of the blocks by teams in different parts of the world.
“We are one of the few digital design companies that can handle a design of this size and complexity and we have several more nearing completion,” said Graham Curran, Sondrel’s CEO and Founder. “A key part of this is our experience of managing the logistics of having teams in seven different locations and coordinating their work. For example, our teams in India and China work in the evenings to maximise the overlap with our teams in Europe.”
Integration and Implementation
Once each block was finished, the big challenge was to bring them all together by creating abstract models of the lower blocks to provide input for the higher blocks so that the size of the part of design being implemented remained manageable. As the chip can run at up to 100 Watts, even the heat output of the different parts of the chip had to be allowed for in the design to prevent hotspots.
Once all the component blocks had been implemented, the whole design was run as a complete unit on a dedicated computer farm consisting of 25 computers, each with 24 CPUs and 1.5 Terabytes of memory, and over 100 software licenses to perform physical validation checks, which took two days.
“This initially started as a design for 28nm technology,” explained Stuart Vernon, Sondrel’s Senior Director of Physical Design. “However, it soon became apparent that, on 28nm, it would either be one very big chip, which would not have been cost-effective, or it would have to be split into two connected chips, which would introduce parasitics and timing issues. So the decision was made to use the 16nm TSMC process node to enable the design to fit onto a single chip at a cost-effective price point.”