Cadence, headquartered in San Jose, Calif., enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company has sales offices, design centres, and research facilities around the world to serve the global electronics industry.
Electronic design is facing two major challenges today: the ever-increasing silicon capacity and rapidly increasing system complexity. Even the global electronic design automation (EDA) industry is evolving to meet those challenges. Here, Martin Lund, senior vice president of R&D for the SoC Realization Group at Cadence Design Systems, recently spoke to Pradeep Chakraborty of EFY about how the company is helping meet these challenges.
Q. What are the challenges faced by electronics and semiconductor companies today?
A. IC designers who work at advanced semiconductor process nodes, such as 20nm and 14nm, will be able to place billions of transistors on a chip, but these nodes will also bring challenges such as double patterning, layout-dependent effects, and new design rules and types of transistors.
Additionally, nearly all system-on-chip (SoC) designs now combine analogue and digital IP blocks, making mixed-signal design and verification a necessity. Since software has become the key differentiator in many electronic products, software must be developed early along with system hardware.
Q. How is the EDA industry evolving to meet the challenges of system capability, power, time-to-market and profitability?
A. Many of today’s design challenges are interdependent. In order to deal with this interdependency, EDA companies must not only address specific, thorny technical issues, but also collaborate closely with ecosystem partners to develop practical and reliable solutions in a reasonable timeframe.
For example: process technology and circuit design interact to affect power consumption; both of those also interact with layout to affect hardware performance; and hardware design interacts with embedded software to determine the overall characteristics of a device, like features, usability, and application support.
Cadence has developed leading design technologies in each of these areas. But as each individual factor becomes more complex, the overall challenge increases even more rapidly.
A crucial part of the solution is for ecosystem partners to manage the scope of interdependencies through collaboration. Instead of each partner spending time and money to develop a universal solution to support all possible permutations of other factors, companies collaborate to define and optimise solutions to manage the interdependencies for the most important scenarios.
Most of the really big successes in the semiconductor industry today are the result of collaboration between software providers, IP and EDA companies, application creators, IC foundries and others.
Q. What are some of the breakthrough solutions Cadence has developed to help customers?
A. For over 20 years, Cadence has developed innovative technologies and breakthrough solutions, enough to earn more than 1,200 patents worldwide, which is more than any other EDA company.
Here are some recent examples:
Comprehensive solutions for 20nm design and below, proven with leading foundries and IP providers, enable custom, mixed-signal, and big digital designs at the most advanced process nodes.
Our industry-leading design infrastructure for 3D-IC IC design was developed and proven in collaboration with a leading foundry. The Virtual System Platform simplifies the creation and use of virtual prototypes before a project commits to hardware design.
New in-circuit acceleration approaches, based on the Incisive and Palladium XP platforms, give engineers the ability to go beyond simulation to accelerate verification of large-scale SoCs, subsystems, and systems.
Q. What has Cadence been doing lately on IP design and innovation in the manufacture of silicon chips (3D-IC)?
A. The Cadence Silicon Realization group did a great job of getting IC design tools ready for 3D-IC design, and as a result Cadence has been involved in many 3D-IC tapeouts.
A key driver for the use of 3D-ICs is the ability to have a faster, low-power interface to DRAM memory. The first generation of that is the JEDEC Wide I/O standard, and Cadence was first to market with a design IP solution for Wide I/O.
Today’s smartphones and tablets have an amazing appetite for memory bandwidth and they need to access that memory using the minimum amount of power. Wide I/O interfaces conveniently solve that problem by offering substantially higher bandwidth than the current-generation technologies, and doing it with less power per bit transferred.
In addition, by using 2.5D or 3D-IC packaging, wide I/O can eliminate the memory package from the system, which allows for smaller, lighter products.
Last year, ST-Ericsson and the CEA-LETI research institute announced a heterogeneous three-die stack that included Cadence design IP for Wide I/O. Creation of the wide I/O design IP used Cadence’s expertise in DRAM, test, design, tools, and IP to craft an optimal solution.
Cadence high-performance, low power memory controller design was modified for the test and manufacturing challenges posed by 3D-ICs. Since then we’ve been working on a silicon interposer-based design and Wide I/O PHY to offer a full range of design IP for Wide I/O, and we will take the steps necessary to support the upcoming higher speeds and greater memory density standards proposed for 3D-IC connected memory.
