Thursday, May 30, 2024

Imec Demonstrates Integrated Forksheet FETs For 2nm Processes

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Imec successfully demonstrates its proposed forksheet FETs for 2nm processes and presents their electrical characterization.

As conventional field effect transistors (FETs) are reaching their operating limits and the design specifications in electronic devices are constantly demanding high performance and efficient semiconductor devices, it is necessary to turn towards new semiconductor device designs. Forksheet FETs were proposed by Imec in late 2019 as the most promising device architecture.

Forksheet FETs fall under the gate-all-around (GAA) category. The devices in this category can enable extreme scaling of the gate lengths. Gate length scaling is crucial to meet today’s high performance computing needs.

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In forksheet FETs, both nFETs and pFETs are integrated on the same structure and the dielectric separates them. This approach is different from currently existing GAA devices that use different devices for pFETs and nFETs. The forksheet FETs allow for tighter spacing between n and p devices, reducing the area. 

Imec recently demonstrated forksheet FETs for 2nm process and the device architecture was found to extend the GAA devices generation with additional scaling and perform beyond 2nm technology node.

Unlike nanosheet devices, these FETs are controlled by a tri-gate forked structure – realized by introducing a dielectric wall in between the p- and nMOS devices before gate patterning.

The device architecture reduces the miller capacitance resulting from a smaller gate-drain overlap. TCAD simulations also show superior performance scalability. Imec, moreover, shows electrical characteristics of the forksheet devices that were successfully integrated by using a 300mm process flow, with gate lengths down to 22nm. Both n and p-FETs were found fully functional and the short channel control was comparable to that of vertically stacked nanosheet devices that were co-integrated on the same wafer.

The gap between the integrated n and p-FETs can be as tight as 17 nm, which is 35% of the spacing in state-of-the-art FinFET technology. This makes forksheet FETs a very promising device architecture .

“From 2022 onwards, it is expected that today’s leading-edge FinFET transistors will gradually give way to vertically stacked nanosheet transistors in high-volume manufacturing, as the FinFET fails to provide enough performance at scaled dimensions,” explains Naoto Horiguchi, Director CMOS Device Technology at Imec, “process limitations will however pose a limit to how close the nanosheet’s n and p devices can be brought together, challenging further cell height reduction. The new forksheet device architecture – which is a natural evolution of the GAA nanosheet device – promises to push this limit, allowing track height scaling from 5T to 4.3T while still offering a performance gain. Alternatively, with a forksheet design, the available space can be used to increase the sheet width and as such further enhance the drive current. Our electrical characterization results confirm that the forksheet is the most promising device architecture to extend the logic and SRAM scaling roadmaps beyond 2nm leveraging the nanosheet integration in a non-disruptive way.”

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