Designs and Validates Power delivery (PDN) solutions for Graphics IP and SoCs. Conducts and participates in the design, development, and verification of on-chip power grid, power gating, VR solutions, power delivery circuits like LDO, BGREFs, Droop Detector for GPU IP/SOC products.
Job includes understanding and developing PDN architecture and integration requirements of IPs and sub-systems to come up with PDN back-end implementation and sign-off specifications. Work with tool vendor to stay up to date with new analysis features and deploy them on complex GPU products.
- Should possess a Bachelor of Engineering or a Master degree of Science/Engineering in the field of Electronics/VLSI.
- Must have hands on experience with IR drop/droop, in-rush-current/powerup analysis and Electromigration analysis.
- 3 to 7 Years of experience in PDN/power grid design, verification, and/or sign-off using industry standard tools.
- Must have design and hands on experience of power grid design & sign-off, droop mitigation techniques or schemes on a production chip is a plus.
- Must have in depth knowledge of active and passive components used in PD domain.
- Experience in any APR tool (ICC/Innovus) along with power integrity analysis and ESD convergence will be added advantage.
- Must be able to work effectively with floorplan, integration and packaging teams to define optimum power grid strategy.