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This position is for a technical contributor (individual) role in the domain of back-end for automating device templates using virtuoso SKILL, and sign-off for TI using ICV/Calibre flows in the Technology Development, RnD team of Intel. In this position, you will be expected to deploy tools/flows methodologies for device/p-cell development, Tape-in, and review post silicon results. You will be working with research team for device/p-cell development and implement floor-plan, placement, routing, extraction and tape-in of various designs. You will be working on integration methodologies of nominal, HV, EHV voltage device templates into IPs. Develop and support python based flows, setup the same for performing regressions on the specified tools as per design flow. You will be expected to provide necessary data in making decisions on tools and methodologies of choice in the associated domains on leading edge process nodes . This role also gives opportunity to work on newest of technology, with key stakeholders in design, central CAD and other projects on similar technologies to enable next generation tools and methodologies in process, extraction, runsets, domains by closely working with both external and internal vendors. You may need to respond to users in design team’s requests or events as they occur, develops solutions to problems utilizing formal education and engineering judgement.
Candidate needs to have Master’s degree (M.Tech/MS) in Electronics Engineering or equivalent qualification from reputed institute with 2+ year experience in Cadence virtuoso SKILL, python, TCL, layout development.. He should have good knowledge of VLSI and basic electronics. Understanding of fabrication and process technology will be added advantage. Any knowledge/experience on C/C++ with data structures an d programming would be plus point.