Tuesday, June 25, 2024

DFM, Layout And Physical Verification Engineer At Intel

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Job Description

This role is for individual technical contributor for physicals sign off methodology development and validation, including flow and tools. Candidate will be expected to drive and influence methodology for dummy fill and physical sign off flow like DRC, LVS , Density and Antenna checks. He/ She will be enabling and validation these flows through rigorous testing by creating innovative testcases covering wide scenarios to avoid any escapes in flow, for leading edge process nodes. The role will give opportunity to work on newest of technology and work with key stakeholders in technology, Design team, CAD teams to drive next generation tools and co-develop methodologies, by closely working with external and internal tool vendors. Role needs creative thinking to find corner cases, work arounds, debug and troubleshooting mindset.


Candidate should have 3+ years of relevant experience, with masters in VLSI/ Microelectronics/Electronics engineering and have worked on industry standard tools for Physical sign off. He /She should be well versed with various options to optimize flow in terms of quality and compute resources. Candidate should have good understanding of rule file/ tech files for these flows. He/ She should have good knowledge of semiconductor physics, process technology, EDA tools and associated challenges for advance technology. He / She should have good scripting skill for automation, like TCL, Perl or Python. Understanding of fabrication and process technology will be added advantage

Location: Bengaluru

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Company: Intel

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