The Memory IP Group (MIP) within the Client Engineering Group (CEG) is looking for a Pre-Silicon Verification Engineer to deliver latest and best in class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products.
In this role you will perform all aspects of the verification flow through simulation and/or emulation.
Performing IP Verification related tasks such as creating test plan, validating design and micro-architectural implementation.
Automating validation tasks to get it done in the most efficient way possible. Analyzing result and help to debug issues in pre-silicon environment at IP, subsystem and SOC level.
The additional responsibilities include:
- development of validation strategies and plans, scoping and driving execution for different area of pre-Si validation.
- provide guidance and help to team members in understanding issues, removing roadblocks and ensuring issue resolution.
- strong demonstration of Intel Cultural values
Candidate must possess a Bachelor or higher of degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science or equivalent with 3-8 years of relevant experience in Design verification, System Verilog and OVM/UVM
Experienced in validation methodology, waveform debug, functional coverage, VCS simulation
Capable of multitasking in dynamic environment with multiple teams from different geo
Solid verbal and written communication skillsExcellent debug and problem solving skills
Preferred Qualifications:Knowledge of computer architecture preferably x86Scripting languages such as Python/ PerlExperience with DDR validation
Inside this Business Group
The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel’s leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.