MIT’s new fabrication trick gives paired chips matching physical IDs for secure, server-less authentication.
In hardware security news, researchers at the Massachusetts Institute of Technology have developed a new chip-processing method that could tighten cryptographic security at the device level by creating paired physical fingerprints on microchips. This technique addresses a longstanding challenge in secure device authentication, eliminating the need for external servers to hold secret key data and could benefit energy-constrained electronics from medical sensors to Internet-of-Things gadgets.
At the heart of the advance is a method for generating a shared physical unclonable function (PUF) across two chips during fabrication. PUFs are unique, hardware-intrinsic fingerprints resulting from tiny, unavoidable variations in semiconductor manufacturing. Traditionally, cryptographic authentication using a PUF requires storing reference responses on a server, which introduces security risks and adds memory and computation overhead.
To overcome this, MIT engineers devised a method to embed a matched PUF on two adjacent chips before they’re cut apart. By strategically placing pairs of transistors along the edge of a silicon wafer and inducing controlled breakdowns using low-cost LEDs, they exploit manufacturing randomness to create highly correlated physical states between the paired chips. After the wafer is diced, each chip carries half of a twin PUF that matches its partner with over 98 % reliability.
This paired PUF enables direct mutual authentication between devices without server-side reference data or external key exchange, strengthening security and simplifying protocol stacks, particularly useful in systems where energy efficiency is critical. For example, an ingestible sensor could authenticate directly with a paired wearable patch, without an intermediary infrastructure.
A key practical advantage of the approach is its compatibility with standard CMOS fabrication, requiring no exotic materials or complex post-processing, potentially easing adoption in industrial chip production. Future refinements aim to embed shared randomness more deeply within transistor states to further harden security at the physical level. By moving cryptographic trust into the physical silicon and removing reliance on external key stores, this work represents a significant step toward secure hardware authentication that’s both energy-lean and robust against conventional attack surfaces.
