The supply voltages generated by these are subjected to large variations. One need not worry about regulation in it, if they have an op-amp that can work over such large range; it avoids any intermediate stage of regulation.

Expandable platforms. It is very important to be able to incorporate new hardware and software solutions to a system in order to produce a better end product. As a result, it is very critical to have a flexible and expandable design platform that is compatible to and can incorporate both new hardware and software solutions, whenever necessary. Microchip’s PIC16(L)F170X and PIC16(L)F171X family of 8-bit microcontrollers offers intelligent analogue and core-independent peripherals (configurable logic cell, complementary output generator and zero crossing detector), providing increased flexibility for designers.

Somsubhro Pal Choudhury of Analog Devices believes that, the wide range of different types and sizes of data, bandwidth availability, reliability and cost considerations will not make a ‘one size fits all’ model. “Customisations and optimisations for each market vertical and sub-vertical would be the key with the industry severely fragmented, at least in this decade,” he adds.

Dedicated processors. There has been a lot of talk about dedicated microcontrollers. Many original equipment manufacturers and fabrication plants are working on process technologies that could create processors optimised for and committed specifically to the analogue implementation in IoT applications.

In-built battery monitoring. As wearable devices are run by small batteries, it is necessary to optimise the use of these power sources. An accurate battery monitoring allows the user to know the exact state of charge of battery and adds intelligence to its usage.

For example, STC3115 battery monitoring IC by STMicroelectronics could give timely alert to the user for turning off the power-consuming blocks when battery is lower than the user-programmed threshold levels.

Innovative technologies driving cutting-edge analogue components
Shrinking the size and increasing performance has always been the challenge in semiconductor industry. The semiconductor industry has been witnessing the lowering of cost and size in the last couple of decades. Process nodes have been going from 45nm down to 28nm to 20nm, and will further go down to 16nm and 10nm in the next decade.

But the manufacturers’ challenge was to achieve spatial, monetary or power efficiencies. Hence, as the limit of Moore’s law reached 28 nm, they had to migrate from planar CMOS to a new process technology. That is when devices using FinFET technology were demonstrated by Taiwan Semiconductor Manufacturing Company.

Multiple fin-height FinFETs. The most advanced semiconductor technology used today can produce around 10 million transistor elements in a chip of size one square centimetre. A new multiple fin-height FinFET process technology has been developed at National Nano Device Laboratories (NDL), National Applied Research Laboratories (NARLabs). It allows up to 20 million transistors in the same place, which is twice the number possible today!

Unlike the traditional field-effect transistors (FETs), where gate controls source-drain current only on one side, the fin field-effect transistor (FinFET) has three-dimensional fork-shaped gate similar to a fish’s fin (hence the name). It can control the source-drain current in the transistor from three sides—left, right and top. In multiple fin-height FinFET, like the name suggests, the fins will have different heights allowing different amount of currents corresponding to associated channel height. This concept lets further reduction in chip area by 20%. Compared to a normal FinFET, the multiple-height FinFET has 20% higher storage capacity and 20% less manufacturing cost.

FD-SOI. STMicroelectronics, along with its partners, introduced a technology known as Fully Depleted Silicon On Insulator (FD-SOI). It is a planar process technology where an ultra-thin layer of insulator (buried oxide or BOX) is positioned on top of the base silicon and then a very thin silicon film implements the transistor channel.

IC etched on graphene. Several manufacturing units have been working on moving from silicon to other alternatives, to get better performance in terms of power, size and cost. These alternates could be based on graphene, nanotubes or various tunnel field-effect transistors (TFETs).

There is on-going research on these and other devices based on electron spin as opposed to electron charge. Researchers at University of California, Santa Barbara, have come up with the concept and demonstration of an integrated circuit design scheme where the transistors and interconnects are monolithically patterned seamlessly (without obvious joints or seams) on a two-dimensional atomically flat sheet of graphene.

The model of etching offers possibilities for extremely energy-efficient, transparent and flexible next-generation green electronics.

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