What is a MOSFET? It’s Types, Working, Circuit, and Applications

A voltage applied to the gate controls the current flowing between drain and source by forming or depleting a conductive channel.

The minimum gate-to-source voltage required to start forming a conductive channel.

The on-state resistance between drain and source when the MOSFET is ON. Lower Rds(on) = lower conduction losses.

A MOSFET designed to fully turn ON at low gate voltages (2.5–5V), making it compatible with microcontrollers.

An inherent diode between drain and source that conducts during reverse polarity. It’s important in motor control, buck converters, and H-bridge designs.

It may turn ON/OFF unpredictably due to noise. Always pull gate HIGH or LOW using a resistor.

To protect against high voltage spikes generated by coils, motors, and relays.

It defines safe limits for voltage, current, and power dissipation to prevent thermal or avalanche damage.

The total charge needed to fully switch the MOSFET ON. Lower Qg = faster switching.

When heat increases Rds(on), causing more heat—leading to device failure.

A gate driver boosts the gate voltage and provides fast current pulses, ensuring optimal switching at high frequencies.

A negative electric field (from the positive gate) attracts electrons to the semiconductor surface and repels holes; the holes experience an electrostatic force pushing them away from the oxide interface. This field causes band bending and, for sufficiently positive gate voltage (NMOS), creates an inversion layer (electron channel) by attracting electrons.

No. The gate is separated from the semiconductor by an insulating gate oxide (ideally SiO₂ or a high-k dielectric). That means no DC current should flow into the gate (very high input impedance). Gate control is capacitive—the gate voltage creates an electric field that modulates channel conductivity.

Historically the gate insulator is silicon dioxide (SiO₂). Modern processes may use high-k dielectrics (e.g., HfO₂) to reduce leakage while increasing capacitance. Aluminum oxide is not the standard gate dielectric in mainstream MOSFET processes.

The gate-to-source voltage (V_GS) relative to the threshold (V_th) determines channel charge. When V_GS > V_th, an inversion layer forms and carriers flow between drain and source. Other factors: channel geometry (W/L), mobility, R_ds(on), temperature, and short-channel effects in scaled devices.

The gate signal switches the device quickly and efficiently, controlling when the MOSFET is in ON (low R_ds(on)) or OFF (cutoff). Proper gate drive amplitude and timing minimize switching losses, reduce EMI, prevent shoot-through in bridges, and ensure reliable thermal behavior. In short: good gate drive = efficient, safe switching.

Switching uses both cutoff (OFF) and the ohmic/linear region (ON) — the device is driven fully ON (low R_ds(on)) or fully OFF. For analog amplification you use the saturation (active) region; but for switching applications you toggle between cutoff and the low-resistance linear/triode ON state.

The oxide electrically isolates the gate from the channel while enabling capacitive coupling so the gate voltage can control the channel. It prevents DC gate leakage and permits formation of the inversion channel by the electric field.

SCE occur as channel length shrinks and include: threshold voltage roll-off, drain-induced barrier lowering (DIBL), increased off-state leakage, velocity saturation, higher electric fields causing hot-carrier effects, and reduced gate control over the channel. These degrade device scaling, require engineering fixes (halo implants, high-k dielectrics, multi-gate structures).

Because the gate draws almost no DC current, it is modeled as a voltage input (open circuit for DC current). The small-signal model uses a dependent current source (g_m·v_gs) from drain to source to show how the input voltage controls output current; the gate node is effectively driven by a voltage source with associated gate capacitances for AC behavior.

Key intrinsic capacitances: C_gs (gate-to-source), C_gd (gate-to-drain, “Miller” capacitance), C_gb (gate-to-body). They determine switching speed, gate charge (Q_g), and cause the Miller effect (slows switching during V_DS transitions). Gate drive design must account for these to control turn-on/off times and switching losses.

The gate terminal controls the device.

The saturation (active) region for analog amplification — the device must be biased so ID depends on V_GS and is relatively independent of V_DS over the operating range.

Gate voltage modulates the surface potential and creates/depletes carriers under the oxide. When V_GS > V_th, a conductive inversion channel forms enabling current from drain to source; increasing V_GS increases channel charge and thus increases drain current (within limits).

Very high input impedance (gate insulated), enabling low drive power; plus fast switching, low conduction losses (when R_ds(on) is low), and easy CMOS integration — making them ideal for digital logic and high-efficiency power electronics.

If the body/substrate is not tied to source, a difference between source and body voltages changes threshold voltage (body effect): V_th increases as source-body voltage becomes more positive (for NMOS), reducing drive and changing device behavior. Important in analog and mixed-signal designs.

In diode mode: check body diode (drain→source shows diode for NMOS), verify no short between gate and drain/source (gate should be open), then apply a small gate charge (or use ohm mode) to see if drain-source conducts when gate is driven. For more thorough testing use curve tracer or transistor-tester to measure V_th, R_ds(on), and leakage.

To operate as a linear resistor, bias the gate so the device is partly on and keep V_DS small so it remains in the triode/linear region. In practice, this means applying a fixed V_GS above threshold and using the device with low V_DS. Tying gate to source makes it OFF; gate tied to drain makes a diode-connected device, not a linear resistor. So you do not tie gate to source; you apply a controlled gate bias.